Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T4,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T4,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T4,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	812645063	649573574	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	812645063	3994826	0	0
GntImpliesValid_A	812645063	3994826	0	0
GrantKnown_A	812645063	649573574	0	0
IdxKnown_A	812645063	649573574	0	0
IndexIsCorrect_A	812645063	3994826	0	0
LockArbDecision_A	812645063	0	0	0
NoReadyValidNoGrant_A	812645063	0	0	0
ReadyAndValidImplyGrant_A	812645063	3994826	0	0
ReqAndReadyImplyGrant_A	812645063	3994826	0	0
ReqImpliesValid_A	812645063	3994826	0	0
ReqStaysHighUntilGranted0_M	812645063	0	0	0
RoundRobin_A	812645063	9	0	974
ValidKnown_A	812645063	649573574	0	0
gen_data_port_assertion.DataFlow_A	812645063	3994826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	649573574	0	0
T1	901	824	0	0
T2	343061	343002	0	0
T3	1414	1345	0	0
T4	1068954	652319	0	0
T5	1085675	723561	0	0
T6	1403	1237	0	0
T7	5370	4350	0	0
T8	2167661	1333060	0	0
T9	12052	11845	0	0
T10	1299971	763086	0	0
T11	529710	256968	0	0
T12	330480	159616	0	0
T13	442774	436096	0	0
T15	0	14648	0	0
T16	0	10131	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	3994826	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	1068954	13312	0	0
T5	1085675	10831	0	0
T6	1403	3	0	0
T7	5370	832	0	0
T8	2167661	17521	0	0
T9	12052	832	0	0
T10	1299971	16022	0	0
T11	875053	9235	0	0
T12	330480	5667	0	0
T13	885548	6327	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	3994826	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	1068954	13312	0	0
T5	1085675	10831	0	0
T6	1403	3	0	0
T7	5370	832	0	0
T8	2167661	17521	0	0
T9	12052	832	0	0
T10	1299971	16022	0	0
T11	875053	9235	0	0
T12	330480	5667	0	0
T13	885548	6327	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	649573574	0	0
T1	901	824	0	0
T2	343061	343002	0	0
T3	1414	1345	0	0
T4	1068954	652319	0	0
T5	1085675	723561	0	0
T6	1403	1237	0	0
T7	5370	4350	0	0
T8	2167661	1333060	0	0
T9	12052	11845	0	0
T10	1299971	763086	0	0
T11	529710	256968	0	0
T12	330480	159616	0	0
T13	442774	436096	0	0
T15	0	14648	0	0
T16	0	10131	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	649573574	0	0
T1	901	824	0	0
T2	343061	343002	0	0
T3	1414	1345	0	0
T4	1068954	652319	0	0
T5	1085675	723561	0	0
T6	1403	1237	0	0
T7	5370	4350	0	0
T8	2167661	1333060	0	0
T9	12052	11845	0	0
T10	1299971	763086	0	0
T11	529710	256968	0	0
T12	330480	159616	0	0
T13	442774	436096	0	0
T15	0	14648	0	0
T16	0	10131	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	3994826	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	1068954	13312	0	0
T5	1085675	10831	0	0
T6	1403	3	0	0
T7	5370	832	0	0
T8	2167661	17521	0	0
T9	12052	832	0	0
T10	1299971	16022	0	0
T11	875053	9235	0	0
T12	330480	5667	0	0
T13	885548	6327	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	3994826	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	1068954	13312	0	0
T5	1085675	10831	0	0
T6	1403	3	0	0
T7	5370	832	0	0
T8	2167661	17521	0	0
T9	12052	832	0	0
T10	1299971	16022	0	0
T11	875053	9235	0	0
T12	330480	5667	0	0
T13	885548	6327	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	3994826	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	1068954	13312	0	0
T5	1085675	10831	0	0
T6	1403	3	0	0
T7	5370	832	0	0
T8	2167661	17521	0	0
T9	12052	832	0	0
T10	1299971	16022	0	0
T11	875053	9235	0	0
T12	330480	5667	0	0
T13	885548	6327	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	3994826	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	1068954	13312	0	0
T5	1085675	10831	0	0
T6	1403	3	0	0
T7	5370	832	0	0
T8	2167661	17521	0	0
T9	12052	832	0	0
T10	1299971	16022	0	0
T11	875053	9235	0	0
T12	330480	5667	0	0
T13	885548	6327	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	9	0	974
T18	643806	1	0	1
T32	0	1	0	0
T43	341572	0	0	1
T50	112978	0	0	1
T51	481985	0	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	260528	0	0	1
T61	155295	0	0	1
T62	18750	0	0	1
T63	172992	0	0	1
T64	283186	0	0	1
T65	33798	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	649573574	0	0
T1	901	824	0	0
T2	343061	343002	0	0
T3	1414	1345	0	0
T4	1068954	652319	0	0
T5	1085675	723561	0	0
T6	1403	1237	0	0
T7	5370	4350	0	0
T8	2167661	1333060	0	0
T9	12052	11845	0	0
T10	1299971	763086	0	0
T11	529710	256968	0	0
T12	330480	159616	0	0
T13	442774	436096	0	0
T15	0	14648	0	0
T16	0	10131	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812645063	3994826	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	1068954	13312	0	0
T5	1085675	10831	0	0
T6	1403	3	0	0
T7	5370	832	0	0
T8	2167661	17521	0	0
T9	12052	832	0	0
T10	1299971	16022	0	0
T11	875053	9235	0	0
T12	330480	5667	0	0
T13	885548	6327	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T4,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	161546146	31625007	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	161546146	673641	0	0
GntImpliesValid_A	161546146	673641	0	0
GrantKnown_A	161546146	31625007	0	0
IdxKnown_A	161546146	31625007	0	0
IndexIsCorrect_A	161546146	673641	0	0
LockArbDecision_A	161546146	0	0	0
NoReadyValidNoGrant_A	161546146	0	0	0
ReadyAndValidImplyGrant_A	161546146	673641	0	0
ReqAndReadyImplyGrant_A	161546146	673641	0	0
ReqImpliesValid_A	161546146	673641	0	0
ReqStaysHighUntilGranted0_M	161546146	0	0	0
RoundRobin_A	161546146	0	0	0
ValidKnown_A	161546146	31625007	0	0
gen_data_port_assertion.DataFlow_A	161546146	673641	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	31625007	0	0
T4	409665	79944	0	0
T5	355166	233296	0	0
T6	80	80	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	152408	0	0
T11	264855	256968	0	0
T12	165240	159616	0	0
T13	442774	256072	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	673641	0	0
T4	409665	3057	0	0
T5	355166	6482	0	0
T6	80	2	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	1269	0	0
T11	264855	6225	0	0
T12	165240	3753	0	0
T13	442774	6192	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	673641	0	0
T4	409665	3057	0	0
T5	355166	6482	0	0
T6	80	2	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	1269	0	0
T11	264855	6225	0	0
T12	165240	3753	0	0
T13	442774	6192	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	31625007	0	0
T4	409665	79944	0	0
T5	355166	233296	0	0
T6	80	80	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	152408	0	0
T11	264855	256968	0	0
T12	165240	159616	0	0
T13	442774	256072	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	31625007	0	0
T4	409665	79944	0	0
T5	355166	233296	0	0
T6	80	80	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	152408	0	0
T11	264855	256968	0	0
T12	165240	159616	0	0
T13	442774	256072	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	673641	0	0
T4	409665	3057	0	0
T5	355166	6482	0	0
T6	80	2	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	1269	0	0
T11	264855	6225	0	0
T12	165240	3753	0	0
T13	442774	6192	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	673641	0	0
T4	409665	3057	0	0
T5	355166	6482	0	0
T6	80	2	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	1269	0	0
T11	264855	6225	0	0
T12	165240	3753	0	0
T13	442774	6192	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	673641	0	0
T4	409665	3057	0	0
T5	355166	6482	0	0
T6	80	2	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	1269	0	0
T11	264855	6225	0	0
T12	165240	3753	0	0
T13	442774	6192	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	673641	0	0
T4	409665	3057	0	0
T5	355166	6482	0	0
T6	80	2	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	1269	0	0
T11	264855	6225	0	0
T12	165240	3753	0	0
T13	442774	6192	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	31625007	0	0
T4	409665	79944	0	0
T5	355166	233296	0	0
T6	80	80	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	152408	0	0
T11	264855	256968	0	0
T12	165240	159616	0	0
T13	442774	256072	0	0
T26	0	343312	0	0
T27	0	109072	0	0
T28	0	61528	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	673641	0	0
T4	409665	3057	0	0
T5	355166	6482	0	0
T6	80	2	0	0
T7	588	0	0	0
T8	830229	0	0	0
T9	128	0	0	0
T10	534219	1269	0	0
T11	264855	6225	0	0
T12	165240	3753	0	0
T13	442774	6192	0	0
T26	0	4440	0	0
T28	0	2756	0	0
T29	0	219	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T4,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T4,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T8,T10
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	161546146	128483375	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	161546146	913106	0	0
GntImpliesValid_A	161546146	913106	0	0
GrantKnown_A	161546146	128483375	0	0
IdxKnown_A	161546146	128483375	0	0
IndexIsCorrect_A	161546146	913106	0	0
LockArbDecision_A	161546146	0	0	0
NoReadyValidNoGrant_A	161546146	0	0	0
ReadyAndValidImplyGrant_A	161546146	913106	0	0
ReqAndReadyImplyGrant_A	161546146	913106	0	0
ReqImpliesValid_A	161546146	913106	0	0
ReqStaysHighUntilGranted0_M	161546146	0	0	0
RoundRobin_A	161546146	0	0	0
ValidKnown_A	161546146	128483375	0	0
gen_data_port_assertion.DataFlow_A	161546146	913106	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	128483375	0	0
T2	169736	169736	0	0
T4	409665	322758	0	0
T5	355166	114994	0	0
T6	80	0	0	0
T7	588	224	0	0
T8	830229	825912	0	0
T9	128	128	0	0
T10	534219	379353	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	0	180024	0	0
T15	0	14648	0	0
T16	0	10131	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	913106	0	0
T4	409665	2892	0	0
T5	355166	0	0	0
T6	80	0	0	0
T7	588	0	0	0
T8	830229	6128	0	0
T9	128	0	0	0
T10	534219	6123	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	442774	135	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	913106	0	0
T4	409665	2892	0	0
T5	355166	0	0	0
T6	80	0	0	0
T7	588	0	0	0
T8	830229	6128	0	0
T9	128	0	0	0
T10	534219	6123	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	442774	135	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	128483375	0	0
T2	169736	169736	0	0
T4	409665	322758	0	0
T5	355166	114994	0	0
T6	80	0	0	0
T7	588	224	0	0
T8	830229	825912	0	0
T9	128	128	0	0
T10	534219	379353	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	0	180024	0	0
T15	0	14648	0	0
T16	0	10131	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	128483375	0	0
T2	169736	169736	0	0
T4	409665	322758	0	0
T5	355166	114994	0	0
T6	80	0	0	0
T7	588	224	0	0
T8	830229	825912	0	0
T9	128	128	0	0
T10	534219	379353	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	0	180024	0	0
T15	0	14648	0	0
T16	0	10131	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	913106	0	0
T4	409665	2892	0	0
T5	355166	0	0	0
T6	80	0	0	0
T7	588	0	0	0
T8	830229	6128	0	0
T9	128	0	0	0
T10	534219	6123	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	442774	135	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	913106	0	0
T4	409665	2892	0	0
T5	355166	0	0	0
T6	80	0	0	0
T7	588	0	0	0
T8	830229	6128	0	0
T9	128	0	0	0
T10	534219	6123	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	442774	135	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	913106	0	0
T4	409665	2892	0	0
T5	355166	0	0	0
T6	80	0	0	0
T7	588	0	0	0
T8	830229	6128	0	0
T9	128	0	0	0
T10	534219	6123	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	442774	135	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	913106	0	0
T4	409665	2892	0	0
T5	355166	0	0	0
T6	80	0	0	0
T7	588	0	0	0
T8	830229	6128	0	0
T9	128	0	0	0
T10	534219	6123	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	442774	135	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	128483375	0	0
T2	169736	169736	0	0
T4	409665	322758	0	0
T5	355166	114994	0	0
T6	80	0	0	0
T7	588	224	0	0
T8	830229	825912	0	0
T9	128	128	0	0
T10	534219	379353	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	0	180024	0	0
T15	0	14648	0	0
T16	0	10131	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161546146	913106	0	0
T4	409665	2892	0	0
T5	355166	0	0	0
T6	80	0	0	0
T7	588	0	0	0
T8	830229	6128	0	0
T9	128	0	0	0
T10	534219	6123	0	0
T11	264855	0	0	0
T12	165240	0	0	0
T13	442774	135	0	0
T36	0	2898	0	0
T40	0	272	0	0
T41	0	4114	0	0
T42	0	7336	0	0
T46	0	8364	0	0
T52	0	4645	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	489552771	489465192	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	489552771	2408079	0	0
GntImpliesValid_A	489552771	2408079	0	0
GrantKnown_A	489552771	489465192	0	0
IdxKnown_A	489552771	489465192	0	0
IndexIsCorrect_A	489552771	2408079	0	0
LockArbDecision_A	489552771	0	0	0
NoReadyValidNoGrant_A	489552771	0	0	0
ReadyAndValidImplyGrant_A	489552771	2408079	0	0
ReqAndReadyImplyGrant_A	489552771	2408079	0	0
ReqImpliesValid_A	489552771	2408079	0	0
ReqStaysHighUntilGranted0_M	489552771	0	0	0
RoundRobin_A	489552771	9	0	974
ValidKnown_A	489552771	489465192	0	0
gen_data_port_assertion.DataFlow_A	489552771	2408079	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	489465192	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	2408079	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	7363	0	0
T5	375343	4349	0	0
T6	1243	1	0	0
T7	4194	832	0	0
T8	507203	11393	0	0
T9	11796	832	0	0
T10	231533	8630	0	0
T11	345343	3010	0	0
T12	0	1914	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	2408079	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	7363	0	0
T5	375343	4349	0	0
T6	1243	1	0	0
T7	4194	832	0	0
T8	507203	11393	0	0
T9	11796	832	0	0
T10	231533	8630	0	0
T11	345343	3010	0	0
T12	0	1914	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	489465192	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	489465192	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	2408079	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	7363	0	0
T5	375343	4349	0	0
T6	1243	1	0	0
T7	4194	832	0	0
T8	507203	11393	0	0
T9	11796	832	0	0
T10	231533	8630	0	0
T11	345343	3010	0	0
T12	0	1914	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	2408079	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	7363	0	0
T5	375343	4349	0	0
T6	1243	1	0	0
T7	4194	832	0	0
T8	507203	11393	0	0
T9	11796	832	0	0
T10	231533	8630	0	0
T11	345343	3010	0	0
T12	0	1914	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	2408079	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	7363	0	0
T5	375343	4349	0	0
T6	1243	1	0	0
T7	4194	832	0	0
T8	507203	11393	0	0
T9	11796	832	0	0
T10	231533	8630	0	0
T11	345343	3010	0	0
T12	0	1914	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	2408079	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	7363	0	0
T5	375343	4349	0	0
T6	1243	1	0	0
T7	4194	832	0	0
T8	507203	11393	0	0
T9	11796	832	0	0
T10	231533	8630	0	0
T11	345343	3010	0	0
T12	0	1914	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	9	0	974
T18	643806	1	0	1
T32	0	1	0	0
T43	341572	0	0	1
T50	112978	0	0	1
T51	481985	0	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	260528	0	0	1
T61	155295	0	0	1
T62	18750	0	0	1
T63	172992	0	0	1
T64	283186	0	0	1
T65	33798	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	489465192	0	0
T1	901	824	0	0
T2	173325	173266	0	0
T3	1414	1345	0	0
T4	249624	249617	0	0
T5	375343	375271	0	0
T6	1243	1157	0	0
T7	4194	4126	0	0
T8	507203	507148	0	0
T9	11796	11717	0	0
T10	231533	231325	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489552771	2408079	0	0
T2	173325	832	0	0
T3	1414	0	0	0
T4	249624	7363	0	0
T5	375343	4349	0	0
T6	1243	1	0	0
T7	4194	832	0	0
T8	507203	11393	0	0
T9	11796	832	0	0
T10	231533	8630	0	0
T11	345343	3010	0	0
T12	0	1914	0	0