Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3287444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3959131

1

T1

2318

T2

892

T3

1564

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4038492	1			T1	2786		T2	6		T3	1371
values[0x0]	1601869	1			T1	493		T2	421		T3	436
values[0x1]	1606214	1			T1	411		T2	469		T3	443

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2342658	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4903917

1

T1

2594

T2

893

T3

1700

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27036	1			T3	6		T6	4		T7	8
valid_sources[0x01]	30600	1			T1	25		T3	3		T7	12
valid_sources[0x02]	25578	1			T1	44		T3	2		T8	37
valid_sources[0x03]	42046	1			T1	40		T3	5		T6	1
valid_sources[0x04]	25355	1			T1	29		T3	3		T6	5
valid_sources[0x05]	27582	1			T1	27		T3	3		T6	1
valid_sources[0x06]	26194	1			T1	2		T7	5		T9	117
valid_sources[0x07]	28467	1			T1	6		T3	18		T6	6
valid_sources[0x08]	28737	1			T1	51		T3	10		T5	26
valid_sources[0x09]	29267	1			T1	1		T3	3		T6	4
valid_sources[0x0a]	30280	1			T1	23		T3	9		T6	9
valid_sources[0x0b]	26300	1			T1	46		T3	6		T6	3
valid_sources[0x0c]	26949	1			T1	31		T3	2		T7	1
valid_sources[0x0d]	26484	1			T1	1		T3	9		T7	1
valid_sources[0x0e]	27219	1			T3	16		T6	4		T9	54
valid_sources[0x0f]	41532	1			T1	1		T3	6		T6	13
valid_sources[0x10]	24974	1			T1	24		T3	13		T6	3
valid_sources[0x11]	23444	1			T3	6		T6	1		T9	27
valid_sources[0x12]	26561	1			T1	3		T3	9		T7	3
valid_sources[0x13]	29254	1			T1	5		T3	6		T6	3
valid_sources[0x14]	26863	1			T1	1		T3	6		T7	1
valid_sources[0x15]	30897	1			T3	13		T6	3		T7	1
valid_sources[0x16]	29865	1			T1	28		T3	29		T6	8
valid_sources[0x17]	30734	1			T1	16		T3	2		T6	3
valid_sources[0x18]	27125	1			T1	28		T3	7		T6	2
valid_sources[0x19]	25725	1			T1	17		T3	26		T6	12
valid_sources[0x1a]	26644	1			T1	9		T3	9		T6	4
valid_sources[0x1b]	26350	1			T1	15		T3	14		T7	6
valid_sources[0x1c]	27434	1			T1	14		T3	2		T7	1
valid_sources[0x1d]	26348	1			T1	5		T3	13		T7	1
valid_sources[0x1e]	28297	1			T1	9		T3	3		T7	2
valid_sources[0x1f]	27346	1			T1	3		T7	8		T9	191
valid_sources[0x20]	31106	1			T1	7		T3	2		T7	4
valid_sources[0x21]	28652	1			T1	11		T3	14		T7	2
valid_sources[0x22]	28104	1			T1	3		T3	27		T6	7
valid_sources[0x23]	25085	1			T1	21		T3	7		T7	2
valid_sources[0x24]	29408	1			T1	59		T3	2		T6	1
valid_sources[0x25]	26383	1			T1	13		T3	2		T6	12
valid_sources[0x26]	27359	1			T1	19		T3	11		T6	7
valid_sources[0x27]	30824	1			T1	4		T3	12		T6	5
valid_sources[0x28]	26047	1			T1	12		T3	17		T6	3
valid_sources[0x29]	30072	1			T1	3		T3	11		T6	9
valid_sources[0x2a]	24483	1			T1	8		T3	6		T7	3
valid_sources[0x2b]	25089	1			T1	17		T7	5		T9	132
valid_sources[0x2c]	28226	1			T1	1		T3	4		T7	8
valid_sources[0x2d]	25202	1			T1	17		T3	5		T6	8
valid_sources[0x2e]	26473	1			T1	30		T3	2		T6	6
valid_sources[0x2f]	26213	1			T1	10		T3	10		T7	1
valid_sources[0x30]	28226	1			T1	36		T3	8		T6	5
valid_sources[0x31]	26501	1			T1	12		T3	4		T7	5
valid_sources[0x32]	29194	1			T1	2		T3	4		T6	3
valid_sources[0x33]	31534	1			T1	27		T3	12		T6	6
valid_sources[0x34]	30182	1			T1	19		T3	20		T7	5
valid_sources[0x35]	28912	1			T1	13		T3	9		T6	4
valid_sources[0x36]	28398	1			T1	8		T3	8		T6	1
valid_sources[0x37]	28662	1			T1	6		T3	1		T6	6
valid_sources[0x38]	29428	1			T1	24		T3	2		T7	8
valid_sources[0x39]	29531	1			T1	2		T3	7		T6	5
valid_sources[0x3a]	25610	1			T1	14		T3	7		T6	7
valid_sources[0x3b]	27888	1			T1	42		T3	7		T6	2
valid_sources[0x3c]	26872	1			T1	2		T3	30		T6	10
valid_sources[0x3d]	25762	1			T3	5		T6	1		T7	2
valid_sources[0x3e]	26078	1			T1	6		T3	10		T6	5
valid_sources[0x3f]	28333	1			T1	14		T3	9		T6	6
valid_sources[0x40]	25888	1			T1	24		T3	13		T6	3
valid_sources[0x41]	28407	1			T3	10		T6	1		T7	5
valid_sources[0x42]	29379	1			T1	7		T3	13		T6	6
valid_sources[0x43]	28963	1			T1	24		T3	14		T6	9
valid_sources[0x44]	37173	1			T1	1		T3	2		T6	6
valid_sources[0x45]	27773	1			T1	10		T3	6		T6	3
valid_sources[0x46]	35577	1			T1	14		T3	4		T6	3
valid_sources[0x47]	25473	1			T1	4		T3	7		T7	4
valid_sources[0x48]	33439	1			T1	25		T3	13		T6	1
valid_sources[0x49]	27542	1			T1	14		T3	6		T6	5
valid_sources[0x4a]	29239	1			T1	23		T3	8		T6	7
valid_sources[0x4b]	30025	1			T1	36		T3	12		T6	5
valid_sources[0x4c]	27067	1			T1	25		T3	14		T7	8
valid_sources[0x4d]	28769	1			T1	10		T3	10		T6	1
valid_sources[0x4e]	29497	1			T1	18		T3	3		T6	2
valid_sources[0x4f]	27454	1			T1	25		T3	8		T6	9
valid_sources[0x50]	28387	1			T1	8		T6	8		T7	6
valid_sources[0x51]	25163	1			T1	6		T3	4		T6	11
valid_sources[0x52]	26172	1			T1	10		T3	15		T6	3
valid_sources[0x53]	25881	1			T3	3		T7	1		T9	98
valid_sources[0x54]	26582	1			T1	2		T3	13		T6	2
valid_sources[0x55]	36966	1			T1	21		T3	18		T6	4
valid_sources[0x56]	27905	1			T1	26		T3	5		T7	10
valid_sources[0x57]	26376	1			T1	29		T3	9		T7	5
valid_sources[0x58]	26907	1			T3	13		T6	9		T7	2
valid_sources[0x59]	27709	1			T1	21		T2	445		T3	8
valid_sources[0x5a]	24710	1			T1	15		T3	7		T7	13
valid_sources[0x5b]	26172	1			T1	1		T3	14		T6	1
valid_sources[0x5c]	26053	1			T1	27		T3	7		T6	4
valid_sources[0x5d]	26821	1			T1	10		T3	5		T6	1
valid_sources[0x5e]	27770	1			T1	15		T3	10		T6	3
valid_sources[0x5f]	26821	1			T1	4		T3	2		T7	5
valid_sources[0x60]	27383	1			T1	10		T3	6		T7	7
valid_sources[0x61]	26403	1			T1	23		T3	11		T6	9
valid_sources[0x62]	26178	1			T3	9		T6	1		T7	4
valid_sources[0x63]	30679	1			T1	9		T3	1		T6	9
valid_sources[0x64]	24683	1			T1	40		T3	16		T6	5
valid_sources[0x65]	28260	1			T1	40		T7	5		T9	92
valid_sources[0x66]	28885	1			T1	16		T3	1		T6	1
valid_sources[0x67]	28995	1			T1	12		T3	12		T7	2
valid_sources[0x68]	28850	1			T1	28		T3	9		T6	7
valid_sources[0x69]	26956	1			T1	35		T3	2		T6	10
valid_sources[0x6a]	25670	1			T1	30		T3	1		T7	2
valid_sources[0x6b]	27401	1			T1	65		T3	4		T7	9
valid_sources[0x6c]	25242	1			T1	29		T3	7		T6	8
valid_sources[0x6d]	50313	1			T3	9		T7	2		T9	119
valid_sources[0x6e]	25966	1			T1	18		T3	12		T6	3
valid_sources[0x6f]	27783	1			T3	6		T6	2		T7	1
valid_sources[0x70]	26126	1			T1	13		T6	10		T7	1
valid_sources[0x71]	31716	1			T1	2		T6	7		T7	1
valid_sources[0x72]	27410	1			T3	5		T6	10		T7	3
valid_sources[0x73]	29355	1			T1	35		T3	14		T6	3
valid_sources[0x74]	26107	1			T1	32		T3	6		T6	1
valid_sources[0x75]	30278	1			T3	43		T6	2		T7	5
valid_sources[0x76]	26705	1			T1	26		T3	8		T6	4
valid_sources[0x77]	31868	1			T1	11		T3	10		T7	1
valid_sources[0x78]	28876	1			T3	12		T7	6		T9	61
valid_sources[0x79]	30525	1			T1	12		T3	9		T6	8
valid_sources[0x7a]	28211	1			T1	9		T3	9		T6	4
valid_sources[0x7b]	25907	1			T1	13		T3	15		T6	2
valid_sources[0x7c]	24835	1			T1	14		T3	6		T6	4
valid_sources[0x7d]	25687	1			T3	7		T6	3		T9	87
valid_sources[0x7e]	29056	1			T1	25		T3	9		T7	7
valid_sources[0x7f]	27480	1			T1	22		T3	10		T6	7
valid_sources[0x80]	31033	1			T1	23		T3	15		T9	91

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1050171

1

T1

1416

T2

5

T3

688

values[0x0]

all_enables

biggest_size

1464282

1

T1

491

T2

419

T3

435

values[0x1]

all_enables

biggest_size

1444678

1

T1

411

T2

468

T3

441