Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3304395

1

T1

1372

T2

4

T3

686

full_word

3958032

1

T1

2318

T2

892

T3

1564

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7262047	1			T1	3690		T2	896		T3	2250
auto[TlIntgErrCmd]	137	1			T105	5		T107	14		T109	13
auto[TlIntgErrData]	118	1			T105	11		T107	6		T109	9
auto[TlIntgErrBoth]	125	1			T105	4		T107	10		T109	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4039117

1

T1

2786

T2

6

T3

1371

auto[1]

3223310

1

T1

904

T2

890

T3

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2988776	1			T1	1370		T2	1		T3	683
auto[TlIntgErrNone]	partial	auto[1]	315278	1			T1	2		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1050170	1			T1	1416		T2	5		T3	688
auto[TlIntgErrNone]	full_word	auto[1]	2907823	1			T1	902		T2	887		T3	876
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T105	2		T107	4		T109	7
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T105	2		T107	7		T109	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T162	1		T163	1		T160	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T105	1		T107	3		T109	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T105	7		T107	2		T109	6
auto[TlIntgErrData]	partial	auto[1]	43	1			T105	4		T107	4		T109	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T159	1		T163	1		T160	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T119	1		T121	1		T159	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T107	1		T109	3		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T105	4		T107	7		T109	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T159	1		T164	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T107	2		T119	1		T121	1