Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441796788	2695608	0	0
DepthKnown_A	441796788	441669757	0	0
RvalidKnown_A	441796788	441669757	0	0
WreadyKnown_A	441796788	441669757	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	2695608	0	0
T1	154922	832	0	0
T2	765971	1663	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	1663	0	0
T7	451259	1667	0	0
T8	55413	0	0	0
T9	668861	13309	0	0
T10	21838	832	0	0
T11	0	2495	0	0
T12	0	832	0	0
T13	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441796788	2969293	0	0
DepthKnown_A	441796788	441669757	0	0
RvalidKnown_A	441796788	441669757	0	0
WreadyKnown_A	441796788	441669757	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	2969293	0	0
T1	154922	3845	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	837	0	0
T8	55413	0	0	0
T9	668861	10816	0	0
T10	21838	832	0	0
T11	0	1664	0	0
T12	0	832	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441796788	186271	0	0
DepthKnown_A	441796788	441669757	0	0
RvalidKnown_A	441796788	441669757	0	0
WreadyKnown_A	441796788	441669757	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	186271	0	0
T9	668861	819	0	0
T10	21838	0	0	0
T11	101949	64	0	0
T12	159469	0	0	0
T13	8975	0	0	0
T14	0	1582	0	0
T15	0	1135	0	0
T24	0	7	0	0
T27	0	334	0	0
T29	180319	717	0	0
T30	1623	0	0	0
T31	161882	893	0	0
T32	2575	15	0	0
T40	0	829	0	0
T41	152162	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441796788	450209	0	0
DepthKnown_A	441796788	441669757	0	0
RvalidKnown_A	441796788	441669757	0	0
WreadyKnown_A	441796788	441669757	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	450209	0	0
T9	668861	819	0	0
T10	21838	0	0	0
T11	101949	64	0	0
T12	159469	0	0	0
T13	8975	0	0	0
T14	0	7089	0	0
T15	0	1129	0	0
T24	0	7	0	0
T27	0	334	0	0
T29	180319	3226	0	0
T30	1623	0	0	0
T31	161882	3681	0	0
T32	2575	35	0	0
T40	0	1271	0	0
T41	152162	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441796788	5756203	0	0
DepthKnown_A	441796788	441669757	0	0
RvalidKnown_A	441796788	441669757	0	0
WreadyKnown_A	441796788	441669757	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	5756203	0	0
T1	154922	2858	0	0
T2	765971	64	0	0
T3	31821	1418	0	0
T4	779	2	0	0
T5	4861	26	0	0
T6	3787	55	0	0
T7	451259	65	0	0
T8	55413	340	0	0
T9	668861	14570	0	0
T10	21838	716	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441796788	13005535	0	0
DepthKnown_A	441796788	441669757	0	0
RvalidKnown_A	441796788	441669757	0	0
WreadyKnown_A	441796788	441669757	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	13005535	0	0
T1	154922	12576	0	0
T2	765971	167	0	0
T3	31821	1418	0	0
T4	779	2	0	0
T5	4861	26	0	0
T6	3787	112	0	0
T7	451259	267	0	0
T8	55413	340	0	0
T9	668861	14325	0	0
T10	21838	716	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441796788	441669757	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0