Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T29,T31
1	0	Covered	T9,T29,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Covered	T9,T29,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T29
1	0	Covered	T9,T11,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T9,T11,T29

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T29
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	716937955	576885779	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	716937955	3502010	0	0
GntImpliesValid_A	716937955	3502010	0	0
GrantKnown_A	716937955	576885779	0	0
IdxKnown_A	716937955	576885779	0	0
IndexIsCorrect_A	716937955	3502010	0	0
LockArbDecision_A	716937955	0	0	0
NoReadyValidNoGrant_A	716937955	0	0	0
ReadyAndValidImplyGrant_A	716937955	3502010	0	0
ReqAndReadyImplyGrant_A	716937955	3502010	0	0
ReqImpliesValid_A	716937955	3502010	0	0
ReqStaysHighUntilGranted0_M	716937955	0	0	0
RoundRobin_A	716937955	6	0	976
ValidKnown_A	716937955	576885779	0	0
gen_data_port_assertion.DataFlow_A	716937955	3502010	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	576885779	0	0
T1	178842	178782	0	0
T2	918171	917736	0	0
T3	40029	39933	0	0
T4	779	722	0	0
T5	6013	5337	0	0
T6	8075	5863	0	0
T7	630413	540590	0	0
T8	170565	108987	0	0
T9	1914677	1283639	0	0
T10	59470	40565	0	0
T11	157654	77587	0	0
T12	156604	156136	0	0
T13	21688	21688	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	3502010	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	1914677	17320	0	0
T10	59470	832	0	0
T11	157654	1995	0	0
T12	313208	832	0	0
T13	43376	832	0	0
T14	0	12134	0	0
T15	0	6819	0	0
T16	0	2421	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	593088	5525	0	0
T31	1078382	3987	0	0
T32	1072	57	0	0
T35	0	4213	0	0
T40	895556	4639	0	0
T41	70568	0	0	0
T56	0	7703	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	3502010	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	1914677	17320	0	0
T10	59470	832	0	0
T11	157654	1995	0	0
T12	313208	832	0	0
T13	43376	832	0	0
T14	0	12134	0	0
T15	0	6819	0	0
T16	0	2421	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	593088	5525	0	0
T31	1078382	3987	0	0
T32	1072	57	0	0
T35	0	4213	0	0
T40	895556	4639	0	0
T41	70568	0	0	0
T56	0	7703	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	576885779	0	0
T1	178842	178782	0	0
T2	918171	917736	0	0
T3	40029	39933	0	0
T4	779	722	0	0
T5	6013	5337	0	0
T6	8075	5863	0	0
T7	630413	540590	0	0
T8	170565	108987	0	0
T9	1914677	1283639	0	0
T10	59470	40565	0	0
T11	157654	77587	0	0
T12	156604	156136	0	0
T13	21688	21688	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	576885779	0	0
T1	178842	178782	0	0
T2	918171	917736	0	0
T3	40029	39933	0	0
T4	779	722	0	0
T5	6013	5337	0	0
T6	8075	5863	0	0
T7	630413	540590	0	0
T8	170565	108987	0	0
T9	1914677	1283639	0	0
T10	59470	40565	0	0
T11	157654	77587	0	0
T12	156604	156136	0	0
T13	21688	21688	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	3502010	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	1914677	17320	0	0
T10	59470	832	0	0
T11	157654	1995	0	0
T12	313208	832	0	0
T13	43376	832	0	0
T14	0	12134	0	0
T15	0	6819	0	0
T16	0	2421	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	593088	5525	0	0
T31	1078382	3987	0	0
T32	1072	57	0	0
T35	0	4213	0	0
T40	895556	4639	0	0
T41	70568	0	0	0
T56	0	7703	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	3502010	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	1914677	17320	0	0
T10	59470	832	0	0
T11	157654	1995	0	0
T12	313208	832	0	0
T13	43376	832	0	0
T14	0	12134	0	0
T15	0	6819	0	0
T16	0	2421	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	593088	5525	0	0
T31	1078382	3987	0	0
T32	1072	57	0	0
T35	0	4213	0	0
T40	895556	4639	0	0
T41	70568	0	0	0
T56	0	7703	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	3502010	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	1914677	17320	0	0
T10	59470	832	0	0
T11	157654	1995	0	0
T12	313208	832	0	0
T13	43376	832	0	0
T14	0	12134	0	0
T15	0	6819	0	0
T16	0	2421	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	593088	5525	0	0
T31	1078382	3987	0	0
T32	1072	57	0	0
T35	0	4213	0	0
T40	895556	4639	0	0
T41	70568	0	0	0
T56	0	7703	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	3502010	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	1914677	17320	0	0
T10	59470	832	0	0
T11	157654	1995	0	0
T12	313208	832	0	0
T13	43376	832	0	0
T14	0	12134	0	0
T15	0	6819	0	0
T16	0	2421	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	593088	5525	0	0
T31	1078382	3987	0	0
T32	1072	57	0	0
T35	0	4213	0	0
T40	895556	4639	0	0
T41	70568	0	0	0
T56	0	7703	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	6	0	976
T36	0	1	0	0
T39	3060	0	0	1
T60	442677	1	0	1
T61	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	271535	0	0	1
T65	26516	0	0	1
T66	1492	0	0	1
T67	141350	0	0	1
T68	43910	0	0	1
T69	15531	0	0	1
T70	135508	0	0	1
T71	1140	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	576885779	0	0
T1	178842	178782	0	0
T2	918171	917736	0	0
T3	40029	39933	0	0
T4	779	722	0	0
T5	6013	5337	0	0
T6	8075	5863	0	0
T7	630413	540590	0	0
T8	170565	108987	0	0
T9	1914677	1283639	0	0
T10	59470	40565	0	0
T11	157654	77587	0	0
T12	156604	156136	0	0
T13	21688	21688	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	716937955	3502010	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	1914677	17320	0	0
T10	59470	832	0	0
T11	157654	1995	0	0
T12	313208	832	0	0
T13	43376	832	0	0
T14	0	12134	0	0
T15	0	6819	0	0
T16	0	2421	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	593088	5525	0	0
T31	1078382	3987	0	0
T32	1072	57	0	0
T35	0	4213	0	0
T40	895556	4639	0	0
T41	70568	0	0	0
T56	0	7703	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T29,T31
1	0	Covered	T9,T29,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Covered	T9,T29,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T29,T31
0	0	1	Unreachable
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T29,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T29,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138605351	29105807	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	138605351	626438	0	0
GntImpliesValid_A	138605351	626438	0	0
GrantKnown_A	138605351	29105807	0	0
IdxKnown_A	138605351	29105807	0	0
IndexIsCorrect_A	138605351	626438	0	0
LockArbDecision_A	138605351	0	0	0
NoReadyValidNoGrant_A	138605351	0	0	0
ReadyAndValidImplyGrant_A	138605351	626438	0	0
ReqAndReadyImplyGrant_A	138605351	626438	0	0
ReqImpliesValid_A	138605351	626438	0	0
ReqStaysHighUntilGranted0_M	138605351	0	0	0
RoundRobin_A	138605351	0	0	0
ValidKnown_A	138605351	29105807	0	0
gen_data_port_assertion.DataFlow_A	138605351	626438	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	29105807	0	0
T5	576	576	0	0
T6	2144	0	0	0
T7	89577	0	0	0
T8	57576	53672	0	0
T9	622908	145056	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	626438	0	0
T9	622908	3640	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	6254	0	0
T15	0	2579	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	296544	2464	0	0
T31	539191	2899	0	0
T32	536	57	0	0
T35	0	4067	0	0
T40	447778	0	0	0
T41	35284	0	0	0
T56	0	1848	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	626438	0	0
T9	622908	3640	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	6254	0	0
T15	0	2579	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	296544	2464	0	0
T31	539191	2899	0	0
T32	536	57	0	0
T35	0	4067	0	0
T40	447778	0	0	0
T41	35284	0	0	0
T56	0	1848	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	29105807	0	0
T5	576	576	0	0
T6	2144	0	0	0
T7	89577	0	0	0
T8	57576	53672	0	0
T9	622908	145056	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	29105807	0	0
T5	576	576	0	0
T6	2144	0	0	0
T7	89577	0	0	0
T8	57576	53672	0	0
T9	622908	145056	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	626438	0	0
T9	622908	3640	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	6254	0	0
T15	0	2579	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	296544	2464	0	0
T31	539191	2899	0	0
T32	536	57	0	0
T35	0	4067	0	0
T40	447778	0	0	0
T41	35284	0	0	0
T56	0	1848	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	626438	0	0
T9	622908	3640	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	6254	0	0
T15	0	2579	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	296544	2464	0	0
T31	539191	2899	0	0
T32	536	57	0	0
T35	0	4067	0	0
T40	447778	0	0	0
T41	35284	0	0	0
T56	0	1848	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	626438	0	0
T9	622908	3640	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	6254	0	0
T15	0	2579	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	296544	2464	0	0
T31	539191	2899	0	0
T32	536	57	0	0
T35	0	4067	0	0
T40	447778	0	0	0
T41	35284	0	0	0
T56	0	1848	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	626438	0	0
T9	622908	3640	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	6254	0	0
T15	0	2579	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	296544	2464	0	0
T31	539191	2899	0	0
T32	536	57	0	0
T35	0	4067	0	0
T40	447778	0	0	0
T41	35284	0	0	0
T56	0	1848	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	29105807	0	0
T5	576	576	0	0
T6	2144	0	0	0
T7	89577	0	0	0
T8	57576	53672	0	0
T9	622908	145056	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	184744	0	0
T15	0	148936	0	0
T24	0	768	0	0
T25	0	792	0	0
T29	296544	64040	0	0
T31	0	288888	0	0
T32	0	536	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	626438	0	0
T9	622908	3640	0	0
T10	18816	0	0	0
T11	78827	0	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	6254	0	0
T15	0	2579	0	0
T24	0	40	0	0
T27	0	1802	0	0
T29	296544	2464	0	0
T31	539191	2899	0	0
T32	536	57	0	0
T35	0	4067	0	0
T40	447778	0	0	0
T41	35284	0	0	0
T56	0	1848	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T29
1	0	Covered	T9,T11,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T9,T11,T29

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T11,T29
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138605351	108137357	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	138605351	749846	0	0
GntImpliesValid_A	138605351	749846	0	0
GrantKnown_A	138605351	108137357	0	0
IdxKnown_A	138605351	108137357	0	0
IndexIsCorrect_A	138605351	749846	0	0
LockArbDecision_A	138605351	0	0	0
NoReadyValidNoGrant_A	138605351	0	0	0
ReadyAndValidImplyGrant_A	138605351	749846	0	0
ReqAndReadyImplyGrant_A	138605351	749846	0	0
ReqImpliesValid_A	138605351	749846	0	0
ReqStaysHighUntilGranted0_M	138605351	0	0	0
RoundRobin_A	138605351	0	0	0
ValidKnown_A	138605351	108137357	0	0
gen_data_port_assertion.DataFlow_A	138605351	749846	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	108137357	0	0
T1	23920	23920	0	0
T2	152200	151862	0	0
T3	8208	8208	0	0
T5	576	0	0	0
T6	2144	2144	0	0
T7	89577	89424	0	0
T8	57576	0	0	0
T9	622908	469781	0	0
T10	18816	18816	0	0
T11	78827	77587	0	0
T12	0	156136	0	0
T13	0	21688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	749846	0	0
T9	622908	988	0	0
T10	18816	0	0	0
T11	78827	263	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	5880	0	0
T15	0	4240	0	0
T16	0	2421	0	0
T29	296544	3061	0	0
T31	539191	1088	0	0
T32	536	0	0	0
T35	0	146	0	0
T40	447778	4639	0	0
T41	35284	0	0	0
T56	0	5855	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	749846	0	0
T9	622908	988	0	0
T10	18816	0	0	0
T11	78827	263	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	5880	0	0
T15	0	4240	0	0
T16	0	2421	0	0
T29	296544	3061	0	0
T31	539191	1088	0	0
T32	536	0	0	0
T35	0	146	0	0
T40	447778	4639	0	0
T41	35284	0	0	0
T56	0	5855	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	108137357	0	0
T1	23920	23920	0	0
T2	152200	151862	0	0
T3	8208	8208	0	0
T5	576	0	0	0
T6	2144	2144	0	0
T7	89577	89424	0	0
T8	57576	0	0	0
T9	622908	469781	0	0
T10	18816	18816	0	0
T11	78827	77587	0	0
T12	0	156136	0	0
T13	0	21688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	108137357	0	0
T1	23920	23920	0	0
T2	152200	151862	0	0
T3	8208	8208	0	0
T5	576	0	0	0
T6	2144	2144	0	0
T7	89577	89424	0	0
T8	57576	0	0	0
T9	622908	469781	0	0
T10	18816	18816	0	0
T11	78827	77587	0	0
T12	0	156136	0	0
T13	0	21688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	749846	0	0
T9	622908	988	0	0
T10	18816	0	0	0
T11	78827	263	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	5880	0	0
T15	0	4240	0	0
T16	0	2421	0	0
T29	296544	3061	0	0
T31	539191	1088	0	0
T32	536	0	0	0
T35	0	146	0	0
T40	447778	4639	0	0
T41	35284	0	0	0
T56	0	5855	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	749846	0	0
T9	622908	988	0	0
T10	18816	0	0	0
T11	78827	263	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	5880	0	0
T15	0	4240	0	0
T16	0	2421	0	0
T29	296544	3061	0	0
T31	539191	1088	0	0
T32	536	0	0	0
T35	0	146	0	0
T40	447778	4639	0	0
T41	35284	0	0	0
T56	0	5855	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	749846	0	0
T9	622908	988	0	0
T10	18816	0	0	0
T11	78827	263	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	5880	0	0
T15	0	4240	0	0
T16	0	2421	0	0
T29	296544	3061	0	0
T31	539191	1088	0	0
T32	536	0	0	0
T35	0	146	0	0
T40	447778	4639	0	0
T41	35284	0	0	0
T56	0	5855	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	749846	0	0
T9	622908	988	0	0
T10	18816	0	0	0
T11	78827	263	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	5880	0	0
T15	0	4240	0	0
T16	0	2421	0	0
T29	296544	3061	0	0
T31	539191	1088	0	0
T32	536	0	0	0
T35	0	146	0	0
T40	447778	4639	0	0
T41	35284	0	0	0
T56	0	5855	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	108137357	0	0
T1	23920	23920	0	0
T2	152200	151862	0	0
T3	8208	8208	0	0
T5	576	0	0	0
T6	2144	2144	0	0
T7	89577	89424	0	0
T8	57576	0	0	0
T9	622908	469781	0	0
T10	18816	18816	0	0
T11	78827	77587	0	0
T12	0	156136	0	0
T13	0	21688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138605351	749846	0	0
T9	622908	988	0	0
T10	18816	0	0	0
T11	78827	263	0	0
T12	156604	0	0	0
T13	21688	0	0	0
T14	0	5880	0	0
T15	0	4240	0	0
T16	0	2421	0	0
T29	296544	3061	0	0
T31	539191	1088	0	0
T32	536	0	0	0
T35	0	146	0	0
T40	447778	4639	0	0
T41	35284	0	0	0
T56	0	5855	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T29
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439727253	439642615	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	439727253	2125726	0	0
GntImpliesValid_A	439727253	2125726	0	0
GrantKnown_A	439727253	439642615	0	0
IdxKnown_A	439727253	439642615	0	0
IndexIsCorrect_A	439727253	2125726	0	0
LockArbDecision_A	439727253	0	0	0
NoReadyValidNoGrant_A	439727253	0	0	0
ReadyAndValidImplyGrant_A	439727253	2125726	0	0
ReqAndReadyImplyGrant_A	439727253	2125726	0	0
ReqImpliesValid_A	439727253	2125726	0	0
ReqStaysHighUntilGranted0_M	439727253	0	0	0
RoundRobin_A	439727253	6	0	976
ValidKnown_A	439727253	439642615	0	0
gen_data_port_assertion.DataFlow_A	439727253	2125726	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	439642615	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	2125726	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	668861	12692	0	0
T10	21838	832	0	0
T11	0	1732	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	2125726	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	668861	12692	0	0
T10	21838	832	0	0
T11	0	1732	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	439642615	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	439642615	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	2125726	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	668861	12692	0	0
T10	21838	832	0	0
T11	0	1732	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	2125726	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	668861	12692	0	0
T10	21838	832	0	0
T11	0	1732	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	2125726	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	668861	12692	0	0
T10	21838	832	0	0
T11	0	1732	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	2125726	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	668861	12692	0	0
T10	21838	832	0	0
T11	0	1732	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	6	0	976
T36	0	1	0	0
T39	3060	0	0	1
T60	442677	1	0	1
T61	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	271535	0	0	1
T65	26516	0	0	1
T66	1492	0	0	1
T67	141350	0	0	1
T68	43910	0	0	1
T69	15531	0	0	1
T70	135508	0	0	1
T71	1140	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	439642615	0	0
T1	154922	154862	0	0
T2	765971	765874	0	0
T3	31821	31725	0	0
T4	779	722	0	0
T5	4861	4761	0	0
T6	3787	3719	0	0
T7	451259	451166	0	0
T8	55413	55315	0	0
T9	668861	668802	0	0
T10	21838	21749	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439727253	2125726	0	0
T1	154922	832	0	0
T2	765971	832	0	0
T3	31821	832	0	0
T4	779	0	0	0
T5	4861	0	0	0
T6	3787	832	0	0
T7	451259	832	0	0
T8	55413	0	0	0
T9	668861	12692	0	0
T10	21838	832	0	0
T11	0	1732	0	0
T12	0	832	0	0
T13	0	832	0	0