Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
3508 |
0 |
0 |
T104 |
10451 |
5 |
0 |
0 |
T105 |
19011 |
1 |
0 |
0 |
T107 |
80573 |
3 |
0 |
0 |
T108 |
14438 |
204 |
0 |
0 |
T109 |
101946 |
4 |
0 |
0 |
T110 |
6226 |
221 |
0 |
0 |
T111 |
4783 |
236 |
0 |
0 |
T119 |
55139 |
2 |
0 |
0 |
T120 |
4117 |
16 |
0 |
0 |
T148 |
35513 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2165 |
0 |
0 |
T104 |
10451 |
13 |
0 |
0 |
T109 |
101946 |
124 |
0 |
0 |
T123 |
7862 |
5 |
0 |
0 |
T125 |
4562 |
4 |
0 |
0 |
T127 |
11326 |
13 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
57 |
0 |
0 |
T149 |
13249 |
28 |
0 |
0 |
T150 |
12163 |
15 |
0 |
0 |
T151 |
91181 |
229 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2188 |
0 |
0 |
T104 |
10451 |
20 |
0 |
0 |
T109 |
101946 |
121 |
0 |
0 |
T123 |
7862 |
6 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
3 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
24 |
0 |
0 |
T149 |
13249 |
36 |
0 |
0 |
T150 |
12163 |
23 |
0 |
0 |
T151 |
91181 |
229 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2618 |
0 |
0 |
T104 |
10451 |
34 |
0 |
0 |
T109 |
101946 |
281 |
0 |
0 |
T123 |
7862 |
17 |
0 |
0 |
T125 |
4562 |
2 |
0 |
0 |
T127 |
11326 |
34 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
51 |
0 |
0 |
T149 |
13249 |
19 |
0 |
0 |
T150 |
12163 |
36 |
0 |
0 |
T151 |
91181 |
220 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
8620 |
0 |
0 |
T104 |
10451 |
143 |
0 |
0 |
T109 |
101946 |
1599 |
0 |
0 |
T123 |
7862 |
120 |
0 |
0 |
T125 |
4562 |
4 |
0 |
0 |
T127 |
11326 |
89 |
0 |
0 |
T141 |
4061 |
7 |
0 |
0 |
T148 |
35513 |
380 |
0 |
0 |
T149 |
13249 |
25 |
0 |
0 |
T150 |
12163 |
27 |
0 |
0 |
T151 |
91181 |
215 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
9625 |
0 |
0 |
T104 |
10451 |
144 |
0 |
0 |
T109 |
101946 |
1994 |
0 |
0 |
T122 |
34869 |
414 |
0 |
0 |
T123 |
7862 |
153 |
0 |
0 |
T127 |
11326 |
362 |
0 |
0 |
T141 |
4061 |
104 |
0 |
0 |
T148 |
35513 |
722 |
0 |
0 |
T149 |
13249 |
58 |
0 |
0 |
T150 |
12163 |
27 |
0 |
0 |
T151 |
91181 |
238 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
10512 |
0 |
0 |
T104 |
10451 |
298 |
0 |
0 |
T109 |
101946 |
1510 |
0 |
0 |
T122 |
34869 |
734 |
0 |
0 |
T123 |
7862 |
130 |
0 |
0 |
T125 |
4562 |
135 |
0 |
0 |
T127 |
11326 |
281 |
0 |
0 |
T148 |
35513 |
638 |
0 |
0 |
T149 |
13249 |
38 |
0 |
0 |
T150 |
12163 |
6 |
0 |
0 |
T151 |
91181 |
255 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
10030 |
0 |
0 |
T104 |
10451 |
160 |
0 |
0 |
T109 |
101946 |
2357 |
0 |
0 |
T123 |
7862 |
104 |
0 |
0 |
T125 |
4562 |
131 |
0 |
0 |
T127 |
11326 |
265 |
0 |
0 |
T141 |
4061 |
4 |
0 |
0 |
T148 |
35513 |
505 |
0 |
0 |
T149 |
13249 |
69 |
0 |
0 |
T150 |
12163 |
41 |
0 |
0 |
T151 |
91181 |
224 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
8956 |
0 |
0 |
T104 |
10451 |
16 |
0 |
0 |
T109 |
101946 |
2004 |
0 |
0 |
T123 |
7862 |
81 |
0 |
0 |
T125 |
4562 |
8 |
0 |
0 |
T127 |
11326 |
268 |
0 |
0 |
T141 |
4061 |
135 |
0 |
0 |
T148 |
35513 |
414 |
0 |
0 |
T149 |
13249 |
38 |
0 |
0 |
T150 |
12163 |
21 |
0 |
0 |
T151 |
91181 |
276 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
9090 |
0 |
0 |
T104 |
10451 |
291 |
0 |
0 |
T109 |
101946 |
1816 |
0 |
0 |
T123 |
7862 |
76 |
0 |
0 |
T125 |
4562 |
88 |
0 |
0 |
T127 |
11326 |
232 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
755 |
0 |
0 |
T149 |
13249 |
41 |
0 |
0 |
T150 |
12163 |
61 |
0 |
0 |
T151 |
91181 |
179 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
9478 |
0 |
0 |
T104 |
10451 |
13 |
0 |
0 |
T109 |
101946 |
2244 |
0 |
0 |
T123 |
7862 |
118 |
0 |
0 |
T125 |
4562 |
118 |
0 |
0 |
T127 |
11326 |
266 |
0 |
0 |
T141 |
4061 |
139 |
0 |
0 |
T148 |
35513 |
472 |
0 |
0 |
T149 |
13249 |
66 |
0 |
0 |
T150 |
12163 |
15 |
0 |
0 |
T151 |
91181 |
222 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
10483 |
0 |
0 |
T104 |
10451 |
99 |
0 |
0 |
T109 |
101946 |
2196 |
0 |
0 |
T123 |
7862 |
107 |
0 |
0 |
T125 |
4562 |
128 |
0 |
0 |
T127 |
11326 |
139 |
0 |
0 |
T141 |
4061 |
9 |
0 |
0 |
T148 |
35513 |
692 |
0 |
0 |
T149 |
13249 |
31 |
0 |
0 |
T150 |
12163 |
14 |
0 |
0 |
T151 |
91181 |
218 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5494 |
0 |
0 |
T104 |
10451 |
68 |
0 |
0 |
T109 |
101946 |
903 |
0 |
0 |
T122 |
34869 |
308 |
0 |
0 |
T123 |
7862 |
53 |
0 |
0 |
T127 |
11326 |
55 |
0 |
0 |
T141 |
4061 |
42 |
0 |
0 |
T148 |
35513 |
311 |
0 |
0 |
T149 |
13249 |
55 |
0 |
0 |
T150 |
12163 |
39 |
0 |
0 |
T151 |
91181 |
235 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5067 |
0 |
0 |
T104 |
10451 |
81 |
0 |
0 |
T109 |
101946 |
1012 |
0 |
0 |
T123 |
7862 |
119 |
0 |
0 |
T125 |
4562 |
52 |
0 |
0 |
T127 |
11326 |
54 |
0 |
0 |
T141 |
4061 |
55 |
0 |
0 |
T148 |
35513 |
353 |
0 |
0 |
T149 |
13249 |
34 |
0 |
0 |
T150 |
12163 |
33 |
0 |
0 |
T151 |
91181 |
231 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4914 |
0 |
0 |
T104 |
10451 |
75 |
0 |
0 |
T109 |
101946 |
581 |
0 |
0 |
T122 |
34869 |
421 |
0 |
0 |
T125 |
4562 |
8 |
0 |
0 |
T127 |
11326 |
163 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
265 |
0 |
0 |
T149 |
13249 |
58 |
0 |
0 |
T150 |
12163 |
5 |
0 |
0 |
T151 |
91181 |
221 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5795 |
0 |
0 |
T104 |
10451 |
50 |
0 |
0 |
T109 |
101946 |
1037 |
0 |
0 |
T123 |
7862 |
106 |
0 |
0 |
T125 |
4562 |
44 |
0 |
0 |
T127 |
11326 |
57 |
0 |
0 |
T141 |
4061 |
42 |
0 |
0 |
T148 |
35513 |
298 |
0 |
0 |
T149 |
13249 |
45 |
0 |
0 |
T150 |
12163 |
54 |
0 |
0 |
T151 |
91181 |
236 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4938 |
0 |
0 |
T104 |
10451 |
141 |
0 |
0 |
T109 |
101946 |
779 |
0 |
0 |
T123 |
7862 |
81 |
0 |
0 |
T125 |
4562 |
46 |
0 |
0 |
T127 |
11326 |
78 |
0 |
0 |
T141 |
4061 |
2 |
0 |
0 |
T148 |
35513 |
211 |
0 |
0 |
T149 |
13249 |
65 |
0 |
0 |
T150 |
12163 |
21 |
0 |
0 |
T151 |
91181 |
222 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5214 |
0 |
0 |
T104 |
10451 |
56 |
0 |
0 |
T109 |
101946 |
647 |
0 |
0 |
T123 |
7862 |
4 |
0 |
0 |
T125 |
4562 |
71 |
0 |
0 |
T127 |
11326 |
11 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
381 |
0 |
0 |
T149 |
13249 |
78 |
0 |
0 |
T150 |
12163 |
30 |
0 |
0 |
T151 |
91181 |
246 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5089 |
0 |
0 |
T104 |
10451 |
112 |
0 |
0 |
T109 |
101946 |
856 |
0 |
0 |
T123 |
7862 |
76 |
0 |
0 |
T125 |
4562 |
39 |
0 |
0 |
T127 |
11326 |
9 |
0 |
0 |
T141 |
4061 |
58 |
0 |
0 |
T148 |
35513 |
245 |
0 |
0 |
T149 |
13249 |
79 |
0 |
0 |
T150 |
12163 |
16 |
0 |
0 |
T151 |
91181 |
228 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4580 |
0 |
0 |
T104 |
10451 |
65 |
0 |
0 |
T109 |
101946 |
774 |
0 |
0 |
T123 |
7862 |
86 |
0 |
0 |
T125 |
4562 |
59 |
0 |
0 |
T127 |
11326 |
103 |
0 |
0 |
T141 |
4061 |
56 |
0 |
0 |
T148 |
35513 |
162 |
0 |
0 |
T149 |
13249 |
37 |
0 |
0 |
T150 |
12163 |
18 |
0 |
0 |
T151 |
91181 |
213 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4827 |
0 |
0 |
T104 |
10451 |
98 |
0 |
0 |
T109 |
101946 |
723 |
0 |
0 |
T122 |
34869 |
401 |
0 |
0 |
T123 |
7862 |
7 |
0 |
0 |
T125 |
4562 |
40 |
0 |
0 |
T127 |
11326 |
62 |
0 |
0 |
T141 |
4061 |
3 |
0 |
0 |
T148 |
35513 |
314 |
0 |
0 |
T149 |
13249 |
17 |
0 |
0 |
T151 |
91181 |
227 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4819 |
0 |
0 |
T104 |
10451 |
21 |
0 |
0 |
T109 |
101946 |
664 |
0 |
0 |
T122 |
34869 |
363 |
0 |
0 |
T123 |
7862 |
43 |
0 |
0 |
T125 |
4562 |
39 |
0 |
0 |
T127 |
11326 |
115 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
255 |
0 |
0 |
T150 |
12163 |
13 |
0 |
0 |
T151 |
91181 |
223 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4785 |
0 |
0 |
T104 |
10451 |
47 |
0 |
0 |
T109 |
101946 |
1032 |
0 |
0 |
T122 |
34869 |
205 |
0 |
0 |
T123 |
7862 |
5 |
0 |
0 |
T127 |
11326 |
44 |
0 |
0 |
T141 |
4061 |
8 |
0 |
0 |
T148 |
35513 |
187 |
0 |
0 |
T149 |
13249 |
75 |
0 |
0 |
T150 |
12163 |
12 |
0 |
0 |
T151 |
91181 |
266 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5111 |
0 |
0 |
T104 |
10451 |
153 |
0 |
0 |
T109 |
101946 |
893 |
0 |
0 |
T123 |
7862 |
108 |
0 |
0 |
T125 |
4562 |
58 |
0 |
0 |
T127 |
11326 |
102 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
298 |
0 |
0 |
T149 |
13249 |
53 |
0 |
0 |
T150 |
12163 |
15 |
0 |
0 |
T151 |
91181 |
216 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4993 |
0 |
0 |
T104 |
10451 |
142 |
0 |
0 |
T109 |
101946 |
870 |
0 |
0 |
T123 |
7862 |
60 |
0 |
0 |
T125 |
4562 |
47 |
0 |
0 |
T127 |
11326 |
19 |
0 |
0 |
T141 |
4061 |
60 |
0 |
0 |
T148 |
35513 |
223 |
0 |
0 |
T149 |
13249 |
30 |
0 |
0 |
T150 |
12163 |
33 |
0 |
0 |
T151 |
91181 |
212 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5021 |
0 |
0 |
T104 |
10451 |
11 |
0 |
0 |
T109 |
101946 |
920 |
0 |
0 |
T123 |
7862 |
5 |
0 |
0 |
T125 |
4562 |
1 |
0 |
0 |
T127 |
11326 |
133 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
281 |
0 |
0 |
T149 |
13249 |
74 |
0 |
0 |
T150 |
12163 |
36 |
0 |
0 |
T151 |
91181 |
217 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4534 |
0 |
0 |
T104 |
10451 |
142 |
0 |
0 |
T109 |
101946 |
770 |
0 |
0 |
T123 |
7862 |
32 |
0 |
0 |
T125 |
4562 |
1 |
0 |
0 |
T127 |
11326 |
7 |
0 |
0 |
T141 |
4061 |
56 |
0 |
0 |
T148 |
35513 |
323 |
0 |
0 |
T149 |
13249 |
38 |
0 |
0 |
T150 |
12163 |
13 |
0 |
0 |
T151 |
91181 |
237 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5063 |
0 |
0 |
T104 |
10451 |
74 |
0 |
0 |
T109 |
101946 |
1130 |
0 |
0 |
T122 |
34869 |
127 |
0 |
0 |
T123 |
7862 |
63 |
0 |
0 |
T125 |
4562 |
45 |
0 |
0 |
T127 |
11326 |
10 |
0 |
0 |
T148 |
35513 |
243 |
0 |
0 |
T149 |
13249 |
13 |
0 |
0 |
T150 |
12163 |
23 |
0 |
0 |
T151 |
91181 |
203 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4885 |
0 |
0 |
T104 |
10451 |
51 |
0 |
0 |
T109 |
101946 |
649 |
0 |
0 |
T123 |
7862 |
51 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
127 |
0 |
0 |
T141 |
4061 |
40 |
0 |
0 |
T148 |
35513 |
291 |
0 |
0 |
T149 |
13249 |
12 |
0 |
0 |
T150 |
12163 |
25 |
0 |
0 |
T151 |
91181 |
218 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4994 |
0 |
0 |
T104 |
10451 |
56 |
0 |
0 |
T109 |
101946 |
758 |
0 |
0 |
T123 |
7862 |
71 |
0 |
0 |
T125 |
4562 |
26 |
0 |
0 |
T127 |
11326 |
64 |
0 |
0 |
T141 |
4061 |
2 |
0 |
0 |
T148 |
35513 |
217 |
0 |
0 |
T149 |
13249 |
50 |
0 |
0 |
T150 |
12163 |
30 |
0 |
0 |
T151 |
91181 |
237 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5321 |
0 |
0 |
T104 |
10451 |
21 |
0 |
0 |
T109 |
101946 |
919 |
0 |
0 |
T123 |
7862 |
4 |
0 |
0 |
T125 |
4562 |
2 |
0 |
0 |
T127 |
11326 |
71 |
0 |
0 |
T141 |
4061 |
44 |
0 |
0 |
T148 |
35513 |
363 |
0 |
0 |
T149 |
13249 |
33 |
0 |
0 |
T150 |
12163 |
40 |
0 |
0 |
T151 |
91181 |
215 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4704 |
0 |
0 |
T104 |
10451 |
15 |
0 |
0 |
T109 |
101946 |
730 |
0 |
0 |
T123 |
7862 |
119 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
114 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
318 |
0 |
0 |
T149 |
13249 |
28 |
0 |
0 |
T150 |
12163 |
16 |
0 |
0 |
T151 |
91181 |
217 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5055 |
0 |
0 |
T104 |
10451 |
62 |
0 |
0 |
T109 |
101946 |
737 |
0 |
0 |
T123 |
7862 |
99 |
0 |
0 |
T125 |
4562 |
3 |
0 |
0 |
T127 |
11326 |
49 |
0 |
0 |
T141 |
4061 |
47 |
0 |
0 |
T148 |
35513 |
187 |
0 |
0 |
T149 |
13249 |
11 |
0 |
0 |
T150 |
12163 |
20 |
0 |
0 |
T151 |
91181 |
246 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5021 |
0 |
0 |
T104 |
10451 |
69 |
0 |
0 |
T109 |
101946 |
983 |
0 |
0 |
T123 |
7862 |
55 |
0 |
0 |
T125 |
4562 |
67 |
0 |
0 |
T127 |
11326 |
98 |
0 |
0 |
T141 |
4061 |
7 |
0 |
0 |
T148 |
35513 |
225 |
0 |
0 |
T149 |
13249 |
58 |
0 |
0 |
T150 |
12163 |
20 |
0 |
0 |
T151 |
91181 |
207 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4809 |
0 |
0 |
T104 |
10451 |
82 |
0 |
0 |
T109 |
101946 |
619 |
0 |
0 |
T122 |
34869 |
298 |
0 |
0 |
T123 |
7862 |
113 |
0 |
0 |
T125 |
4562 |
4 |
0 |
0 |
T127 |
11326 |
119 |
0 |
0 |
T141 |
4061 |
39 |
0 |
0 |
T148 |
35513 |
226 |
0 |
0 |
T149 |
13249 |
59 |
0 |
0 |
T151 |
91181 |
235 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
5125 |
0 |
0 |
T104 |
10451 |
47 |
0 |
0 |
T109 |
101946 |
1038 |
0 |
0 |
T123 |
7862 |
9 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
57 |
0 |
0 |
T141 |
4061 |
50 |
0 |
0 |
T148 |
35513 |
160 |
0 |
0 |
T149 |
13249 |
47 |
0 |
0 |
T150 |
12163 |
26 |
0 |
0 |
T151 |
91181 |
261 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2323 |
0 |
0 |
T104 |
10451 |
29 |
0 |
0 |
T109 |
101946 |
153 |
0 |
0 |
T122 |
34869 |
43 |
0 |
0 |
T123 |
7862 |
15 |
0 |
0 |
T127 |
11326 |
2 |
0 |
0 |
T141 |
4061 |
3 |
0 |
0 |
T148 |
35513 |
43 |
0 |
0 |
T149 |
13249 |
50 |
0 |
0 |
T150 |
12163 |
16 |
0 |
0 |
T151 |
91181 |
224 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2449 |
0 |
0 |
T104 |
10451 |
18 |
0 |
0 |
T109 |
101946 |
179 |
0 |
0 |
T123 |
7862 |
20 |
0 |
0 |
T125 |
4562 |
3 |
0 |
0 |
T127 |
11326 |
25 |
0 |
0 |
T141 |
4061 |
2 |
0 |
0 |
T148 |
35513 |
27 |
0 |
0 |
T149 |
13249 |
41 |
0 |
0 |
T150 |
12163 |
43 |
0 |
0 |
T151 |
91181 |
232 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2332 |
0 |
0 |
T104 |
10451 |
23 |
0 |
0 |
T109 |
101946 |
181 |
0 |
0 |
T123 |
7862 |
6 |
0 |
0 |
T125 |
4562 |
2 |
0 |
0 |
T127 |
11326 |
18 |
0 |
0 |
T141 |
4061 |
3 |
0 |
0 |
T148 |
35513 |
50 |
0 |
0 |
T149 |
13249 |
64 |
0 |
0 |
T150 |
12163 |
25 |
0 |
0 |
T151 |
91181 |
215 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2411 |
0 |
0 |
T104 |
10451 |
24 |
0 |
0 |
T109 |
101946 |
167 |
0 |
0 |
T123 |
7862 |
17 |
0 |
0 |
T125 |
4562 |
8 |
0 |
0 |
T127 |
11326 |
10 |
0 |
0 |
T141 |
4061 |
7 |
0 |
0 |
T148 |
35513 |
33 |
0 |
0 |
T149 |
13249 |
30 |
0 |
0 |
T150 |
12163 |
41 |
0 |
0 |
T151 |
91181 |
211 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2866 |
0 |
0 |
T104 |
10451 |
25 |
0 |
0 |
T109 |
101946 |
281 |
0 |
0 |
T123 |
7862 |
17 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
11 |
0 |
0 |
T141 |
4061 |
23 |
0 |
0 |
T148 |
35513 |
75 |
0 |
0 |
T149 |
13249 |
46 |
0 |
0 |
T150 |
12163 |
29 |
0 |
0 |
T151 |
91181 |
188 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
4910 |
0 |
0 |
T14 |
120606 |
19 |
0 |
0 |
T15 |
278958 |
0 |
0 |
0 |
T19 |
0 |
13 |
0 |
0 |
T21 |
0 |
12 |
0 |
0 |
T22 |
0 |
31 |
0 |
0 |
T23 |
946 |
0 |
0 |
0 |
T24 |
2580 |
0 |
0 |
0 |
T25 |
5406 |
0 |
0 |
0 |
T26 |
986 |
0 |
0 |
0 |
T27 |
236399 |
0 |
0 |
0 |
T28 |
9263 |
0 |
0 |
0 |
T33 |
0 |
34 |
0 |
0 |
T34 |
14456 |
0 |
0 |
0 |
T35 |
163860 |
0 |
0 |
0 |
T152 |
0 |
6 |
0 |
0 |
T153 |
0 |
11 |
0 |
0 |
T154 |
0 |
26 |
0 |
0 |
T155 |
0 |
24 |
0 |
0 |
T156 |
0 |
28 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2475 |
0 |
0 |
T104 |
10451 |
20 |
0 |
0 |
T109 |
101946 |
186 |
0 |
0 |
T122 |
34869 |
54 |
0 |
0 |
T123 |
7862 |
7 |
0 |
0 |
T127 |
11326 |
14 |
0 |
0 |
T141 |
4061 |
7 |
0 |
0 |
T148 |
35513 |
51 |
0 |
0 |
T149 |
13249 |
41 |
0 |
0 |
T150 |
12163 |
19 |
0 |
0 |
T151 |
91181 |
211 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2318 |
0 |
0 |
T104 |
10451 |
20 |
0 |
0 |
T109 |
101946 |
161 |
0 |
0 |
T123 |
7862 |
17 |
0 |
0 |
T125 |
4562 |
3 |
0 |
0 |
T127 |
11326 |
13 |
0 |
0 |
T141 |
4061 |
4 |
0 |
0 |
T148 |
35513 |
50 |
0 |
0 |
T149 |
13249 |
22 |
0 |
0 |
T150 |
12163 |
29 |
0 |
0 |
T151 |
91181 |
202 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2296 |
0 |
0 |
T104 |
10451 |
10 |
0 |
0 |
T109 |
101946 |
153 |
0 |
0 |
T122 |
34869 |
40 |
0 |
0 |
T127 |
11326 |
14 |
0 |
0 |
T141 |
4061 |
9 |
0 |
0 |
T148 |
35513 |
36 |
0 |
0 |
T149 |
13249 |
21 |
0 |
0 |
T150 |
12163 |
16 |
0 |
0 |
T151 |
91181 |
224 |
0 |
0 |
T157 |
5142 |
10 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2021 |
0 |
0 |
T104 |
10451 |
16 |
0 |
0 |
T109 |
101946 |
128 |
0 |
0 |
T122 |
34869 |
38 |
0 |
0 |
T123 |
7862 |
6 |
0 |
0 |
T125 |
4562 |
3 |
0 |
0 |
T127 |
11326 |
15 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
40 |
0 |
0 |
T150 |
12163 |
31 |
0 |
0 |
T151 |
91181 |
240 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2289 |
0 |
0 |
T104 |
10451 |
15 |
0 |
0 |
T109 |
101946 |
120 |
0 |
0 |
T123 |
7862 |
11 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
9 |
0 |
0 |
T141 |
4061 |
4 |
0 |
0 |
T148 |
35513 |
32 |
0 |
0 |
T149 |
13249 |
16 |
0 |
0 |
T150 |
12163 |
11 |
0 |
0 |
T151 |
91181 |
238 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2294 |
0 |
0 |
T104 |
10451 |
13 |
0 |
0 |
T109 |
101946 |
113 |
0 |
0 |
T123 |
7862 |
7 |
0 |
0 |
T125 |
4562 |
4 |
0 |
0 |
T127 |
11326 |
10 |
0 |
0 |
T141 |
4061 |
3 |
0 |
0 |
T148 |
35513 |
39 |
0 |
0 |
T149 |
13249 |
9 |
0 |
0 |
T150 |
12163 |
40 |
0 |
0 |
T151 |
91181 |
226 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2949 |
0 |
0 |
T104 |
10451 |
57 |
0 |
0 |
T109 |
101946 |
313 |
0 |
0 |
T123 |
7862 |
10 |
0 |
0 |
T125 |
4562 |
1 |
0 |
0 |
T127 |
11326 |
43 |
0 |
0 |
T141 |
4061 |
6 |
0 |
0 |
T148 |
35513 |
102 |
0 |
0 |
T149 |
13249 |
25 |
0 |
0 |
T150 |
12163 |
6 |
0 |
0 |
T151 |
91181 |
211 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2211 |
0 |
0 |
T104 |
10451 |
25 |
0 |
0 |
T109 |
101946 |
132 |
0 |
0 |
T122 |
34869 |
38 |
0 |
0 |
T123 |
7862 |
2 |
0 |
0 |
T127 |
11326 |
9 |
0 |
0 |
T141 |
4061 |
7 |
0 |
0 |
T148 |
35513 |
24 |
0 |
0 |
T149 |
13249 |
54 |
0 |
0 |
T150 |
12163 |
24 |
0 |
0 |
T151 |
91181 |
258 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2940 |
0 |
0 |
T104 |
10451 |
38 |
0 |
0 |
T109 |
101946 |
309 |
0 |
0 |
T123 |
7862 |
17 |
0 |
0 |
T125 |
4562 |
3 |
0 |
0 |
T127 |
11326 |
46 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
81 |
0 |
0 |
T149 |
13249 |
48 |
0 |
0 |
T150 |
12163 |
20 |
0 |
0 |
T151 |
91181 |
253 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2463 |
0 |
0 |
T104 |
10451 |
38 |
0 |
0 |
T109 |
101946 |
173 |
0 |
0 |
T123 |
7862 |
12 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
4 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
68 |
0 |
0 |
T149 |
13249 |
8 |
0 |
0 |
T150 |
12163 |
17 |
0 |
0 |
T151 |
91181 |
198 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2204 |
0 |
0 |
T104 |
10451 |
8 |
0 |
0 |
T109 |
101946 |
98 |
0 |
0 |
T123 |
7862 |
16 |
0 |
0 |
T125 |
4562 |
1 |
0 |
0 |
T127 |
11326 |
20 |
0 |
0 |
T141 |
4061 |
9 |
0 |
0 |
T148 |
35513 |
41 |
0 |
0 |
T149 |
13249 |
25 |
0 |
0 |
T150 |
12163 |
17 |
0 |
0 |
T151 |
91181 |
206 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2087 |
0 |
0 |
T104 |
10451 |
14 |
0 |
0 |
T109 |
101946 |
139 |
0 |
0 |
T122 |
34869 |
32 |
0 |
0 |
T125 |
4562 |
7 |
0 |
0 |
T127 |
11326 |
4 |
0 |
0 |
T148 |
35513 |
29 |
0 |
0 |
T149 |
13249 |
17 |
0 |
0 |
T150 |
12163 |
6 |
0 |
0 |
T151 |
91181 |
218 |
0 |
0 |
T157 |
5142 |
9 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2262 |
0 |
0 |
T104 |
10451 |
2 |
0 |
0 |
T109 |
101946 |
117 |
0 |
0 |
T122 |
34869 |
34 |
0 |
0 |
T123 |
7862 |
2 |
0 |
0 |
T125 |
4562 |
2 |
0 |
0 |
T127 |
11326 |
11 |
0 |
0 |
T141 |
4061 |
9 |
0 |
0 |
T148 |
35513 |
32 |
0 |
0 |
T149 |
13249 |
16 |
0 |
0 |
T151 |
91181 |
253 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2313 |
0 |
0 |
T104 |
10451 |
7 |
0 |
0 |
T109 |
101946 |
129 |
0 |
0 |
T123 |
7862 |
5 |
0 |
0 |
T125 |
4562 |
9 |
0 |
0 |
T127 |
11326 |
9 |
0 |
0 |
T141 |
4061 |
1 |
0 |
0 |
T148 |
35513 |
55 |
0 |
0 |
T149 |
13249 |
50 |
0 |
0 |
T150 |
12163 |
5 |
0 |
0 |
T151 |
91181 |
213 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2227 |
0 |
0 |
T104 |
10451 |
20 |
0 |
0 |
T109 |
101946 |
123 |
0 |
0 |
T123 |
7862 |
12 |
0 |
0 |
T125 |
4562 |
10 |
0 |
0 |
T127 |
11326 |
1 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
29 |
0 |
0 |
T149 |
13249 |
51 |
0 |
0 |
T150 |
12163 |
21 |
0 |
0 |
T151 |
91181 |
223 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441796788 |
2243 |
0 |
0 |
T104 |
10451 |
14 |
0 |
0 |
T109 |
101946 |
146 |
0 |
0 |
T123 |
7862 |
6 |
0 |
0 |
T125 |
4562 |
5 |
0 |
0 |
T127 |
11326 |
19 |
0 |
0 |
T141 |
4061 |
5 |
0 |
0 |
T148 |
35513 |
40 |
0 |
0 |
T149 |
13249 |
45 |
0 |
0 |
T150 |
12163 |
26 |
0 |
0 |
T151 |
91181 |
253 |
0 |
0 |