Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3825435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4368052

1

T1

19824

T2

896

T3

3994

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4480418	1			T1	20919		T2	54		T3	733
values[0x0]	1855403	1			T1	9747		T2	466		T3	1774
values[0x1]	1857666	1			T1	9682		T2	410		T3	1764

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2702953	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5490534

1

T1

26115

T2

907

T3

4048

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29347	1			T1	203		T3	21		T4	18
valid_sources[0x01]	33379	1			T1	158		T3	18		T4	25
valid_sources[0x02]	30587	1			T1	144		T3	20		T4	15
valid_sources[0x03]	32622	1			T1	184		T3	13		T4	19
valid_sources[0x04]	35641	1			T1	193		T3	11		T4	19
valid_sources[0x05]	31041	1			T1	138		T3	13		T4	10
valid_sources[0x06]	32803	1			T1	136		T3	11		T4	15
valid_sources[0x07]	27999	1			T1	148		T3	17		T4	17
valid_sources[0x08]	34969	1			T1	203		T3	23		T4	24
valid_sources[0x09]	37917	1			T1	158		T3	26		T4	17
valid_sources[0x0a]	29884	1			T1	180		T3	16		T4	16
valid_sources[0x0b]	33248	1			T1	153		T3	11		T4	16
valid_sources[0x0c]	32635	1			T1	152		T3	20		T4	12
valid_sources[0x0d]	29923	1			T1	139		T3	8		T4	16
valid_sources[0x0e]	29268	1			T1	139		T3	18		T4	16
valid_sources[0x0f]	35093	1			T1	150		T3	16		T4	15
valid_sources[0x10]	30167	1			T1	156		T3	16		T4	18
valid_sources[0x11]	33760	1			T1	148		T3	14		T4	23
valid_sources[0x12]	32584	1			T1	170		T3	14		T4	22
valid_sources[0x13]	33376	1			T1	197		T3	22		T4	19
valid_sources[0x14]	29094	1			T1	143		T3	14		T4	23
valid_sources[0x15]	29615	1			T1	145		T3	16		T4	19
valid_sources[0x16]	31726	1			T1	176		T3	11		T4	19
valid_sources[0x17]	30773	1			T1	178		T3	11		T4	16
valid_sources[0x18]	41423	1			T1	153		T3	10		T4	18
valid_sources[0x19]	29699	1			T1	106		T3	15		T4	25
valid_sources[0x1a]	33431	1			T1	148		T3	15		T4	16
valid_sources[0x1b]	32758	1			T1	181		T3	13		T4	16
valid_sources[0x1c]	30712	1			T1	130		T3	23		T4	13
valid_sources[0x1d]	32709	1			T1	144		T3	14		T4	13
valid_sources[0x1e]	28637	1			T1	151		T2	281		T3	18
valid_sources[0x1f]	38467	1			T1	204		T3	14		T4	19
valid_sources[0x20]	29213	1			T1	172		T3	16		T4	30
valid_sources[0x21]	32398	1			T1	154		T3	8		T4	15
valid_sources[0x22]	34701	1			T1	127		T3	18		T4	18
valid_sources[0x23]	27295	1			T1	169		T3	12		T4	11
valid_sources[0x24]	29441	1			T1	156		T3	16		T4	15
valid_sources[0x25]	29354	1			T1	125		T3	18		T4	16
valid_sources[0x26]	29844	1			T1	168		T3	22		T4	21
valid_sources[0x27]	33163	1			T1	120		T3	16		T4	13
valid_sources[0x28]	32534	1			T1	160		T3	8		T4	12
valid_sources[0x29]	32360	1			T1	182		T3	22		T4	16
valid_sources[0x2a]	36392	1			T1	140		T3	23		T4	22
valid_sources[0x2b]	45139	1			T1	202		T3	20		T4	15
valid_sources[0x2c]	29699	1			T1	180		T3	15		T4	13
valid_sources[0x2d]	30316	1			T1	203		T3	14		T4	19
valid_sources[0x2e]	32137	1			T1	133		T3	12		T4	19
valid_sources[0x2f]	31423	1			T1	122		T3	17		T4	15
valid_sources[0x30]	31264	1			T1	143		T3	14		T4	17
valid_sources[0x31]	30096	1			T1	150		T3	21		T4	19
valid_sources[0x32]	32958	1			T1	182		T3	14		T4	23
valid_sources[0x33]	32328	1			T1	148		T3	19		T4	18
valid_sources[0x34]	30544	1			T1	159		T3	17		T4	22
valid_sources[0x35]	31564	1			T1	176		T3	13		T4	22
valid_sources[0x36]	29670	1			T1	108		T3	22		T4	18
valid_sources[0x37]	34225	1			T1	154		T3	16		T4	18
valid_sources[0x38]	29611	1			T1	106		T3	11		T4	21
valid_sources[0x39]	32726	1			T1	122		T3	23		T4	24
valid_sources[0x3a]	33163	1			T1	174		T3	11		T4	20
valid_sources[0x3b]	29376	1			T1	112		T2	22		T3	23
valid_sources[0x3c]	31627	1			T1	165		T3	12		T4	15
valid_sources[0x3d]	30740	1			T1	186		T3	16		T4	18
valid_sources[0x3e]	31694	1			T1	147		T3	14		T4	26
valid_sources[0x3f]	29497	1			T1	141		T3	19		T4	9
valid_sources[0x40]	30403	1			T1	152		T3	21		T4	15
valid_sources[0x41]	33139	1			T1	130		T3	22		T4	20
valid_sources[0x42]	31346	1			T1	208		T3	16		T4	13
valid_sources[0x43]	30687	1			T1	192		T3	24		T4	20
valid_sources[0x44]	30945	1			T1	135		T3	20		T4	12
valid_sources[0x45]	31283	1			T1	154		T3	17		T4	24
valid_sources[0x46]	30389	1			T1	147		T3	19		T4	18
valid_sources[0x47]	30141	1			T1	134		T3	18		T4	17
valid_sources[0x48]	31979	1			T1	184		T3	17		T4	18
valid_sources[0x49]	30527	1			T1	208		T3	17		T4	18
valid_sources[0x4a]	30838	1			T1	150		T2	27		T3	16
valid_sources[0x4b]	31762	1			T1	125		T3	12		T4	20
valid_sources[0x4c]	32428	1			T1	113		T3	19		T4	14
valid_sources[0x4d]	32090	1			T1	226		T3	13		T4	14
valid_sources[0x4e]	32639	1			T1	186		T3	9		T4	16
valid_sources[0x4f]	46606	1			T1	151		T3	11		T4	16
valid_sources[0x50]	30574	1			T1	153		T3	19		T4	17
valid_sources[0x51]	30458	1			T1	169		T3	20		T4	18
valid_sources[0x52]	29787	1			T1	99		T3	15		T4	14
valid_sources[0x53]	30500	1			T1	169		T3	15		T4	15
valid_sources[0x54]	32135	1			T1	127		T3	9		T4	20
valid_sources[0x55]	31882	1			T1	168		T3	16		T4	24
valid_sources[0x56]	32041	1			T1	145		T3	15		T4	24
valid_sources[0x57]	31218	1			T1	188		T3	11		T4	20
valid_sources[0x58]	29179	1			T1	161		T3	13		T4	23
valid_sources[0x59]	27629	1			T1	171		T3	17		T4	17
valid_sources[0x5a]	29888	1			T1	124		T3	17		T4	13
valid_sources[0x5b]	32218	1			T1	163		T3	10		T4	20
valid_sources[0x5c]	31399	1			T1	163		T3	15		T4	14
valid_sources[0x5d]	28537	1			T1	168		T3	14		T4	15
valid_sources[0x5e]	33128	1			T1	193		T3	23		T4	17
valid_sources[0x5f]	30420	1			T1	173		T3	14		T4	24
valid_sources[0x60]	31719	1			T1	161		T3	16		T4	14
valid_sources[0x61]	30461	1			T1	200		T3	22		T4	27
valid_sources[0x62]	35945	1			T1	162		T3	17		T4	16
valid_sources[0x63]	31836	1			T1	163		T3	17		T4	15
valid_sources[0x64]	32897	1			T1	164		T3	16		T4	17
valid_sources[0x65]	29941	1			T1	126		T3	26		T4	23
valid_sources[0x66]	37420	1			T1	135		T3	25		T4	20
valid_sources[0x67]	28662	1			T1	158		T3	10		T4	14
valid_sources[0x68]	30327	1			T1	121		T3	25		T4	15
valid_sources[0x69]	31146	1			T1	149		T3	18		T4	15
valid_sources[0x6a]	31110	1			T1	147		T3	16		T4	20
valid_sources[0x6b]	31196	1			T1	162		T3	16		T4	14
valid_sources[0x6c]	30905	1			T1	136		T3	15		T4	13
valid_sources[0x6d]	33417	1			T1	189		T3	14		T4	13
valid_sources[0x6e]	33515	1			T1	171		T3	14		T4	18
valid_sources[0x6f]	36062	1			T1	163		T3	16		T4	11
valid_sources[0x70]	31882	1			T1	152		T2	15		T3	17
valid_sources[0x71]	33899	1			T1	138		T3	21		T4	7
valid_sources[0x72]	29394	1			T1	165		T3	17		T4	13
valid_sources[0x73]	30745	1			T1	161		T2	6		T3	22
valid_sources[0x74]	30456	1			T1	159		T3	15		T4	21
valid_sources[0x75]	34438	1			T1	136		T3	17		T4	12
valid_sources[0x76]	31423	1			T1	143		T3	23		T4	21
valid_sources[0x77]	32646	1			T1	133		T3	16		T4	22
valid_sources[0x78]	28762	1			T1	158		T3	26		T4	14
valid_sources[0x79]	33054	1			T1	144		T3	17		T4	10
valid_sources[0x7a]	30755	1			T1	114		T3	6		T4	21
valid_sources[0x7b]	31643	1			T1	161		T3	5		T4	12
valid_sources[0x7c]	29948	1			T1	172		T3	17		T4	21
valid_sources[0x7d]	29334	1			T1	124		T3	20		T4	21
valid_sources[0x7e]	31269	1			T1	163		T3	16		T4	14
valid_sources[0x7f]	51979	1			T1	159		T3	23		T4	13
valid_sources[0x80]	32692	1			T1	141		T3	9		T4	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1017084

1

T1

2377

T2

22

T3

478

values[0x0]

all_enables

biggest_size

1687328

1

T1

8798

T2

465

T3

1765

values[0x1]

all_enables

biggest_size

1663640

1

T1

8649

T2

409

T3

1751