Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3845158

1

T1

20524

T2

34

T3

277

full_word

4367018

1

T1

19824

T2

896

T3

3994

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8211806	1			T1	40348		T2	930		T3	4271
auto[TlIntgErrCmd]	110	1			T95	3		T96	1		T97	11
auto[TlIntgErrData]	134	1			T95	3		T96	3		T97	9
auto[TlIntgErrBoth]	126	1			T95	4		T96	6		T97	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4481943

1

T1

20919

T2

54

T3

733

auto[1]

3730233

1

T1

19429

T2

876

T3

3538

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3464655	1			T1	18542		T2	32		T3	255
auto[TlIntgErrNone]	partial	auto[1]	380160	1			T1	1982		T2	2		T3	22
auto[TlIntgErrNone]	full_word	auto[0]	1017126	1			T1	2377		T2	22		T3	478
auto[TlIntgErrNone]	full_word	auto[1]	3349865	1			T1	17447		T2	874		T3	3516
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T95	3		T97	3		T98	4
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T96	1		T97	7		T98	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T97	1		T116	1		T190	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T98	1		T116	1		T191	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T95	3		T96	1		T97	2
auto[TlIntgErrData]	partial	auto[1]	64	1			T96	2		T97	6		T98	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T97	1		T98	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T116	1		T192	1		T190	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T95	2		T97	3		T98	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T95	2		T96	6		T97	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T97	1		T116	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T97	1		T98	1		T191	1