Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454345317	2964303	0	0
DepthKnown_A	454345317	454213038	0	0
RvalidKnown_A	454345317	454213038	0	0
WreadyKnown_A	454345317	454213038	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	2964303	0	0
T1	251839	13327	0	0
T2	26913	832	0	0
T3	285000	5831	0	0
T4	77548	1863	0	0
T5	822759	0	0	0
T6	2520	0	0	0
T7	9390	0	0	0
T8	22818	832	0	0
T9	292657	9980	0	0
T10	288205	1663	0	0
T11	0	11654	0	0
T12	0	832	0	0
T13	0	2495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454345317	3252508	0	0
DepthKnown_A	454345317	454213038	0	0
RvalidKnown_A	454345317	454213038	0	0
WreadyKnown_A	454345317	454213038	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	3252508	0	0
T1	251839	27018	0	0
T2	26913	832	0	0
T3	285000	3338	0	0
T4	77548	1353	0	0
T5	822759	0	0	0
T6	2520	0	0	0
T7	9390	0	0	0
T8	22818	2655	0	0
T9	292657	13922	0	0
T10	288205	832	0	0
T11	0	19074	0	0
T12	0	832	0	0
T13	0	4663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454345317	190668	0	0
DepthKnown_A	454345317	454213038	0	0
RvalidKnown_A	454345317	454213038	0	0
WreadyKnown_A	454345317	454213038	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	190668	0	0
T1	251839	463	0	0
T2	26913	0	0	0
T3	285000	224	0	0
T4	77548	0	0	0
T5	822759	0	0	0
T6	2520	27	0	0
T7	9390	8	0	0
T8	22818	0	0	0
T9	292657	751	0	0
T10	288205	0	0	0
T11	0	1000	0	0
T12	0	2	0	0
T13	0	142	0	0
T23	0	184	0	0
T24	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454345317	462337	0	0
DepthKnown_A	454345317	454213038	0	0
RvalidKnown_A	454345317	454213038	0	0
WreadyKnown_A	454345317	454213038	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	462337	0	0
T1	251839	2115	0	0
T2	26913	0	0	0
T3	285000	992	0	0
T4	77548	0	0	0
T5	822759	0	0	0
T6	2520	27	0	0
T7	9390	8	0	0
T8	22818	0	0	0
T9	292657	2411	0	0
T10	288205	0	0	0
T11	0	3084	0	0
T12	0	2	0	0
T13	0	628	0	0
T23	0	184	0	0
T24	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454345317	6527953	0	0
DepthKnown_A	454345317	454213038	0	0
RvalidKnown_A	454345317	454213038	0	0
WreadyKnown_A	454345317	454213038	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	6527953	0	0
T1	251839	33545	0	0
T2	26913	98	0	0
T3	285000	721	0	0
T4	77548	3181	0	0
T5	822759	814	0	0
T6	2520	160	0	0
T7	9390	1290	0	0
T8	22818	56	0	0
T9	292657	5397	0	0
T10	288205	543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454345317	14600800	0	0
DepthKnown_A	454345317	454213038	0	0
RvalidKnown_A	454345317	454213038	0	0
WreadyKnown_A	454345317	454213038	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	14600800	0	0
T1	251839	136254	0	0
T2	26913	98	0	0
T3	285000	2635	0	0
T4	77548	8968	0	0
T5	822759	814	0	0
T6	2520	160	0	0
T7	9390	1290	0	0
T8	22818	168	0	0
T9	292657	15508	0	0
T10	288205	543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454345317	454213038	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0