Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T1,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	758144121	603659974	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	758144121	3765910	0	0
GntImpliesValid_A	758144121	3765910	0	0
GrantKnown_A	758144121	603659974	0	0
IdxKnown_A	758144121	603659974	0	0
IndexIsCorrect_A	758144121	3765910	0	0
LockArbDecision_A	758144121	0	0	0
NoReadyValidNoGrant_A	758144121	0	0	0
ReadyAndValidImplyGrant_A	758144121	3765910	0	0
ReqAndReadyImplyGrant_A	758144121	3765910	0	0
ReqImpliesValid_A	758144121	3765910	0	0
ReqStaysHighUntilGranted0_M	758144121	0	0	0
RoundRobin_A	758144121	4	0	976
ValidKnown_A	758144121	603659974	0	0
gen_data_port_assertion.DataFlow_A	758144121	3765910	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	603659974	0	0
T1	1084113	664030	0	0
T2	36709	31736	0	0
T3	816078	549419	0	0
T4	98912	88136	0	0
T5	1033147	923379	0	0
T6	6536	4450	0	0
T7	12718	10979	0	0
T8	128672	75429	0	0
T9	1224479	755651	0	0
T10	400445	344228	0	0
T11	0	717373	0	0
T12	0	105540	0	0
T13	0	228237	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	3765910	0	0
T1	1084113	13387	0	0
T2	36709	832	0	0
T3	816078	6885	0	0
T4	98912	1344	0	0
T5	1033147	0	0	0
T6	6536	159	0	0
T7	12718	112	0	0
T8	128672	832	0	0
T9	1224479	12366	0	0
T10	400445	854	0	0
T11	0	16090	0	0
T12	0	14	0	0
T13	0	740	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0
T45	0	250	0	0
T46	0	264	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	3765910	0	0
T1	1084113	13387	0	0
T2	36709	832	0	0
T3	816078	6885	0	0
T4	98912	1344	0	0
T5	1033147	0	0	0
T6	6536	159	0	0
T7	12718	112	0	0
T8	128672	832	0	0
T9	1224479	12366	0	0
T10	400445	854	0	0
T11	0	16090	0	0
T12	0	14	0	0
T13	0	740	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0
T45	0	250	0	0
T46	0	264	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	603659974	0	0
T1	1084113	664030	0	0
T2	36709	31736	0	0
T3	816078	549419	0	0
T4	98912	88136	0	0
T5	1033147	923379	0	0
T6	6536	4450	0	0
T7	12718	10979	0	0
T8	128672	75429	0	0
T9	1224479	755651	0	0
T10	400445	344228	0	0
T11	0	717373	0	0
T12	0	105540	0	0
T13	0	228237	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	603659974	0	0
T1	1084113	664030	0	0
T2	36709	31736	0	0
T3	816078	549419	0	0
T4	98912	88136	0	0
T5	1033147	923379	0	0
T6	6536	4450	0	0
T7	12718	10979	0	0
T8	128672	75429	0	0
T9	1224479	755651	0	0
T10	400445	344228	0	0
T11	0	717373	0	0
T12	0	105540	0	0
T13	0	228237	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	3765910	0	0
T1	1084113	13387	0	0
T2	36709	832	0	0
T3	816078	6885	0	0
T4	98912	1344	0	0
T5	1033147	0	0	0
T6	6536	159	0	0
T7	12718	112	0	0
T8	128672	832	0	0
T9	1224479	12366	0	0
T10	400445	854	0	0
T11	0	16090	0	0
T12	0	14	0	0
T13	0	740	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0
T45	0	250	0	0
T46	0	264	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	3765910	0	0
T1	1084113	13387	0	0
T2	36709	832	0	0
T3	816078	6885	0	0
T4	98912	1344	0	0
T5	1033147	0	0	0
T6	6536	159	0	0
T7	12718	112	0	0
T8	128672	832	0	0
T9	1224479	12366	0	0
T10	400445	854	0	0
T11	0	16090	0	0
T12	0	14	0	0
T13	0	740	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0
T45	0	250	0	0
T46	0	264	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	3765910	0	0
T1	1084113	13387	0	0
T2	36709	832	0	0
T3	816078	6885	0	0
T4	98912	1344	0	0
T5	1033147	0	0	0
T6	6536	159	0	0
T7	12718	112	0	0
T8	128672	832	0	0
T9	1224479	12366	0	0
T10	400445	854	0	0
T11	0	16090	0	0
T12	0	14	0	0
T13	0	740	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0
T45	0	250	0	0
T46	0	264	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	3765910	0	0
T1	1084113	13387	0	0
T2	36709	832	0	0
T3	816078	6885	0	0
T4	98912	1344	0	0
T5	1033147	0	0	0
T6	6536	159	0	0
T7	12718	112	0	0
T8	128672	832	0	0
T9	1224479	12366	0	0
T10	400445	854	0	0
T11	0	16090	0	0
T12	0	14	0	0
T13	0	740	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0
T45	0	250	0	0
T46	0	264	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	4	0	976
T47	204054	2	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	146642	0	0	1
T51	25713	0	0	1
T52	191457	0	0	1
T53	1102	0	0	1
T54	3115	0	0	1
T55	425318	0	0	1
T56	875363	0	0	1
T57	146938	0	0	1
T58	74851	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	603659974	0	0
T1	1084113	664030	0	0
T2	36709	31736	0	0
T3	816078	549419	0	0
T4	98912	88136	0	0
T5	1033147	923379	0	0
T6	6536	4450	0	0
T7	12718	10979	0	0
T8	128672	75429	0	0
T9	1224479	755651	0	0
T10	400445	344228	0	0
T11	0	717373	0	0
T12	0	105540	0	0
T13	0	228237	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758144121	3765910	0	0
T1	1084113	13387	0	0
T2	36709	832	0	0
T3	816078	6885	0	0
T4	98912	1344	0	0
T5	1033147	0	0	0
T6	6536	159	0	0
T7	12718	112	0	0
T8	128672	832	0	0
T9	1224479	12366	0	0
T10	400445	854	0	0
T11	0	16090	0	0
T12	0	14	0	0
T13	0	740	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0
T45	0	250	0	0
T46	0	264	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T1,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153019152	29208973	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153019152	665782	0	0
GntImpliesValid_A	153019152	665782	0	0
GrantKnown_A	153019152	29208973	0	0
IdxKnown_A	153019152	29208973	0	0
IndexIsCorrect_A	153019152	665782	0	0
LockArbDecision_A	153019152	0	0	0
NoReadyValidNoGrant_A	153019152	0	0	0
ReadyAndValidImplyGrant_A	153019152	665782	0	0
ReqAndReadyImplyGrant_A	153019152	665782	0	0
ReqImpliesValid_A	153019152	665782	0	0
ReqStaysHighUntilGranted0_M	153019152	0	0	0
RoundRobin_A	153019152	0	0	0
ValidKnown_A	153019152	29208973	0	0
gen_data_port_assertion.DataFlow_A	153019152	665782	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	29208973	0	0
T1	416137	44136	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	100696	0	0
T6	2008	2008	0	0
T7	1664	1664	0	0
T8	52927	0	0	0
T9	465911	154648	0	0
T10	56120	0	0	0
T11	0	111272	0	0
T13	0	39088	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	665782	0	0
T1	416137	1943	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	117	0	0
T7	1664	69	0	0
T8	52927	0	0	0
T9	465911	2556	0	0
T10	56120	0	0	0
T11	0	4601	0	0
T13	0	477	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T45	0	250	0	0
T46	0	264	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	665782	0	0
T1	416137	1943	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	117	0	0
T7	1664	69	0	0
T8	52927	0	0	0
T9	465911	2556	0	0
T10	56120	0	0	0
T11	0	4601	0	0
T13	0	477	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T45	0	250	0	0
T46	0	264	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	29208973	0	0
T1	416137	44136	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	100696	0	0
T6	2008	2008	0	0
T7	1664	1664	0	0
T8	52927	0	0	0
T9	465911	154648	0	0
T10	56120	0	0	0
T11	0	111272	0	0
T13	0	39088	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	29208973	0	0
T1	416137	44136	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	100696	0	0
T6	2008	2008	0	0
T7	1664	1664	0	0
T8	52927	0	0	0
T9	465911	154648	0	0
T10	56120	0	0	0
T11	0	111272	0	0
T13	0	39088	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	665782	0	0
T1	416137	1943	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	117	0	0
T7	1664	69	0	0
T8	52927	0	0	0
T9	465911	2556	0	0
T10	56120	0	0	0
T11	0	4601	0	0
T13	0	477	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T45	0	250	0	0
T46	0	264	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	665782	0	0
T1	416137	1943	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	117	0	0
T7	1664	69	0	0
T8	52927	0	0	0
T9	465911	2556	0	0
T10	56120	0	0	0
T11	0	4601	0	0
T13	0	477	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T45	0	250	0	0
T46	0	264	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	665782	0	0
T1	416137	1943	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	117	0	0
T7	1664	69	0	0
T8	52927	0	0	0
T9	465911	2556	0	0
T10	56120	0	0	0
T11	0	4601	0	0
T13	0	477	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T45	0	250	0	0
T46	0	264	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	665782	0	0
T1	416137	1943	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	117	0	0
T7	1664	69	0	0
T8	52927	0	0	0
T9	465911	2556	0	0
T10	56120	0	0	0
T11	0	4601	0	0
T13	0	477	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T45	0	250	0	0
T46	0	264	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	29208973	0	0
T1	416137	44136	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	100696	0	0
T6	2008	2008	0	0
T7	1664	1664	0	0
T8	52927	0	0	0
T9	465911	154648	0	0
T10	56120	0	0	0
T11	0	111272	0	0
T13	0	39088	0	0
T22	0	648	0	0
T23	0	22776	0	0
T28	0	77248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	665782	0	0
T1	416137	1943	0	0
T2	4898	0	0	0
T3	265539	0	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	117	0	0
T7	1664	69	0	0
T8	52927	0	0	0
T9	465911	2556	0	0
T10	56120	0	0	0
T11	0	4601	0	0
T13	0	477	0	0
T16	0	4225	0	0
T23	0	1014	0	0
T45	0	250	0	0
T46	0	264	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153019152	122435442	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	153019152	791829	0	0
GntImpliesValid_A	153019152	791829	0	0
GrantKnown_A	153019152	122435442	0	0
IdxKnown_A	153019152	122435442	0	0
IndexIsCorrect_A	153019152	791829	0	0
LockArbDecision_A	153019152	0	0	0
NoReadyValidNoGrant_A	153019152	0	0	0
ReadyAndValidImplyGrant_A	153019152	791829	0	0
ReqAndReadyImplyGrant_A	153019152	791829	0	0
ReqImpliesValid_A	153019152	791829	0	0
ReqStaysHighUntilGranted0_M	153019152	0	0	0
RoundRobin_A	153019152	0	0	0
ValidKnown_A	153019152	122435442	0	0
gen_data_port_assertion.DataFlow_A	153019152	791829	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	122435442	0	0
T1	416137	368060	0	0
T2	4898	4898	0	0
T3	265539	264517	0	0
T4	10682	10682	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	52690	0	0
T9	465911	308408	0	0
T10	56120	56120	0	0
T11	0	606101	0	0
T12	0	105540	0	0
T13	0	189149	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	791829	0	0
T1	416137	1136	0	0
T2	4898	0	0	0
T3	265539	3317	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	0	0	0
T9	465911	1559	0	0
T10	56120	14	0	0
T11	0	1036	0	0
T12	0	14	0	0
T13	0	263	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	791829	0	0
T1	416137	1136	0	0
T2	4898	0	0	0
T3	265539	3317	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	0	0	0
T9	465911	1559	0	0
T10	56120	14	0	0
T11	0	1036	0	0
T12	0	14	0	0
T13	0	263	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	122435442	0	0
T1	416137	368060	0	0
T2	4898	4898	0	0
T3	265539	264517	0	0
T4	10682	10682	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	52690	0	0
T9	465911	308408	0	0
T10	56120	56120	0	0
T11	0	606101	0	0
T12	0	105540	0	0
T13	0	189149	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	122435442	0	0
T1	416137	368060	0	0
T2	4898	4898	0	0
T3	265539	264517	0	0
T4	10682	10682	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	52690	0	0
T9	465911	308408	0	0
T10	56120	56120	0	0
T11	0	606101	0	0
T12	0	105540	0	0
T13	0	189149	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	791829	0	0
T1	416137	1136	0	0
T2	4898	0	0	0
T3	265539	3317	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	0	0	0
T9	465911	1559	0	0
T10	56120	14	0	0
T11	0	1036	0	0
T12	0	14	0	0
T13	0	263	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	791829	0	0
T1	416137	1136	0	0
T2	4898	0	0	0
T3	265539	3317	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	0	0	0
T9	465911	1559	0	0
T10	56120	14	0	0
T11	0	1036	0	0
T12	0	14	0	0
T13	0	263	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	791829	0	0
T1	416137	1136	0	0
T2	4898	0	0	0
T3	265539	3317	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	0	0	0
T9	465911	1559	0	0
T10	56120	14	0	0
T11	0	1036	0	0
T12	0	14	0	0
T13	0	263	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	791829	0	0
T1	416137	1136	0	0
T2	4898	0	0	0
T3	265539	3317	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	0	0	0
T9	465911	1559	0	0
T10	56120	14	0	0
T11	0	1036	0	0
T12	0	14	0	0
T13	0	263	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	122435442	0	0
T1	416137	368060	0	0
T2	4898	4898	0	0
T3	265539	264517	0	0
T4	10682	10682	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	52690	0	0
T9	465911	308408	0	0
T10	56120	56120	0	0
T11	0	606101	0	0
T12	0	105540	0	0
T13	0	189149	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153019152	791829	0	0
T1	416137	1136	0	0
T2	4898	0	0	0
T3	265539	3317	0	0
T4	10682	0	0	0
T5	105194	0	0	0
T6	2008	0	0	0
T7	1664	0	0	0
T8	52927	0	0	0
T9	465911	1559	0	0
T10	56120	14	0	0
T11	0	1036	0	0
T12	0	14	0	0
T13	0	263	0	0
T24	0	79	0	0
T38	0	8584	0	0
T39	0	1874	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452105817	452015559	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	452105817	2308299	0	0
GntImpliesValid_A	452105817	2308299	0	0
GrantKnown_A	452105817	452015559	0	0
IdxKnown_A	452105817	452015559	0	0
IndexIsCorrect_A	452105817	2308299	0	0
LockArbDecision_A	452105817	0	0	0
NoReadyValidNoGrant_A	452105817	0	0	0
ReadyAndValidImplyGrant_A	452105817	2308299	0	0
ReqAndReadyImplyGrant_A	452105817	2308299	0	0
ReqImpliesValid_A	452105817	2308299	0	0
ReqStaysHighUntilGranted0_M	452105817	0	0	0
RoundRobin_A	452105817	4	0	976
ValidKnown_A	452105817	452015559	0	0
gen_data_port_assertion.DataFlow_A	452105817	2308299	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	452015559	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	2308299	0	0
T1	251839	10308	0	0
T2	26913	832	0	0
T3	285000	3568	0	0
T4	77548	1344	0	0
T5	822759	0	0	0
T6	2520	42	0	0
T7	9390	43	0	0
T8	22818	832	0	0
T9	292657	8251	0	0
T10	288205	840	0	0
T11	0	10453	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	2308299	0	0
T1	251839	10308	0	0
T2	26913	832	0	0
T3	285000	3568	0	0
T4	77548	1344	0	0
T5	822759	0	0	0
T6	2520	42	0	0
T7	9390	43	0	0
T8	22818	832	0	0
T9	292657	8251	0	0
T10	288205	840	0	0
T11	0	10453	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	452015559	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	452015559	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	2308299	0	0
T1	251839	10308	0	0
T2	26913	832	0	0
T3	285000	3568	0	0
T4	77548	1344	0	0
T5	822759	0	0	0
T6	2520	42	0	0
T7	9390	43	0	0
T8	22818	832	0	0
T9	292657	8251	0	0
T10	288205	840	0	0
T11	0	10453	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	2308299	0	0
T1	251839	10308	0	0
T2	26913	832	0	0
T3	285000	3568	0	0
T4	77548	1344	0	0
T5	822759	0	0	0
T6	2520	42	0	0
T7	9390	43	0	0
T8	22818	832	0	0
T9	292657	8251	0	0
T10	288205	840	0	0
T11	0	10453	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	2308299	0	0
T1	251839	10308	0	0
T2	26913	832	0	0
T3	285000	3568	0	0
T4	77548	1344	0	0
T5	822759	0	0	0
T6	2520	42	0	0
T7	9390	43	0	0
T8	22818	832	0	0
T9	292657	8251	0	0
T10	288205	840	0	0
T11	0	10453	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	2308299	0	0
T1	251839	10308	0	0
T2	26913	832	0	0
T3	285000	3568	0	0
T4	77548	1344	0	0
T5	822759	0	0	0
T6	2520	42	0	0
T7	9390	43	0	0
T8	22818	832	0	0
T9	292657	8251	0	0
T10	288205	840	0	0
T11	0	10453	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	4	0	976
T47	204054	2	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	146642	0	0	1
T51	25713	0	0	1
T52	191457	0	0	1
T53	1102	0	0	1
T54	3115	0	0	1
T55	425318	0	0	1
T56	875363	0	0	1
T57	146938	0	0	1
T58	74851	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	452015559	0	0
T1	251839	251834	0	0
T2	26913	26838	0	0
T3	285000	284902	0	0
T4	77548	77454	0	0
T5	822759	822683	0	0
T6	2520	2442	0	0
T7	9390	9315	0	0
T8	22818	22739	0	0
T9	292657	292595	0	0
T10	288205	288108	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452105817	2308299	0	0
T1	251839	10308	0	0
T2	26913	832	0	0
T3	285000	3568	0	0
T4	77548	1344	0	0
T5	822759	0	0	0
T6	2520	42	0	0
T7	9390	43	0	0
T8	22818	832	0	0
T9	292657	8251	0	0
T10	288205	840	0	0
T11	0	10453	0	0