Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3889 |
0 |
0 |
T95 |
10140 |
1 |
0 |
0 |
T97 |
28491 |
2 |
0 |
0 |
T98 |
53445 |
3 |
0 |
0 |
T99 |
5713 |
85 |
0 |
0 |
T100 |
4398 |
1 |
0 |
0 |
T101 |
5006 |
193 |
0 |
0 |
T102 |
14664 |
140 |
0 |
0 |
T112 |
26406 |
1 |
0 |
0 |
T113 |
4221 |
2 |
0 |
0 |
T114 |
54284 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1960 |
0 |
0 |
T115 |
9565 |
8 |
0 |
0 |
T124 |
4051 |
6 |
0 |
0 |
T134 |
112339 |
797 |
0 |
0 |
T159 |
181252 |
452 |
0 |
0 |
T160 |
13427 |
49 |
0 |
0 |
T161 |
21727 |
84 |
0 |
0 |
T162 |
13391 |
40 |
0 |
0 |
T163 |
14711 |
15 |
0 |
0 |
T164 |
6232 |
8 |
0 |
0 |
T165 |
7521 |
6 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1985 |
0 |
0 |
T115 |
9565 |
6 |
0 |
0 |
T124 |
4051 |
9 |
0 |
0 |
T131 |
4330 |
5 |
0 |
0 |
T134 |
112339 |
784 |
0 |
0 |
T159 |
181252 |
393 |
0 |
0 |
T160 |
13427 |
22 |
0 |
0 |
T161 |
21727 |
104 |
0 |
0 |
T162 |
13391 |
33 |
0 |
0 |
T163 |
14711 |
31 |
0 |
0 |
T164 |
6232 |
8 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2195 |
0 |
0 |
T115 |
9565 |
7 |
0 |
0 |
T124 |
4051 |
12 |
0 |
0 |
T134 |
112339 |
774 |
0 |
0 |
T159 |
181252 |
407 |
0 |
0 |
T160 |
13427 |
57 |
0 |
0 |
T161 |
21727 |
40 |
0 |
0 |
T162 |
13391 |
46 |
0 |
0 |
T163 |
14711 |
41 |
0 |
0 |
T164 |
6232 |
6 |
0 |
0 |
T165 |
7521 |
12 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
7186 |
0 |
0 |
T99 |
5713 |
7 |
0 |
0 |
T115 |
9565 |
11 |
0 |
0 |
T124 |
4051 |
130 |
0 |
0 |
T131 |
4330 |
47 |
0 |
0 |
T134 |
112339 |
816 |
0 |
0 |
T159 |
181252 |
425 |
0 |
0 |
T160 |
13427 |
64 |
0 |
0 |
T161 |
21727 |
60 |
0 |
0 |
T162 |
13391 |
9 |
0 |
0 |
T163 |
14711 |
211 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
6640 |
0 |
0 |
T115 |
9565 |
87 |
0 |
0 |
T124 |
4051 |
4 |
0 |
0 |
T131 |
4330 |
40 |
0 |
0 |
T134 |
112339 |
787 |
0 |
0 |
T159 |
181252 |
430 |
0 |
0 |
T160 |
13427 |
51 |
0 |
0 |
T161 |
21727 |
78 |
0 |
0 |
T162 |
13391 |
61 |
0 |
0 |
T163 |
14711 |
108 |
0 |
0 |
T164 |
6232 |
133 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
6837 |
0 |
0 |
T115 |
9565 |
71 |
0 |
0 |
T124 |
4051 |
125 |
0 |
0 |
T134 |
112339 |
804 |
0 |
0 |
T159 |
181252 |
477 |
0 |
0 |
T160 |
13427 |
88 |
0 |
0 |
T161 |
21727 |
105 |
0 |
0 |
T162 |
13391 |
18 |
0 |
0 |
T163 |
14711 |
241 |
0 |
0 |
T164 |
6232 |
4 |
0 |
0 |
T165 |
7521 |
269 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
5723 |
0 |
0 |
T115 |
9565 |
81 |
0 |
0 |
T124 |
4051 |
81 |
0 |
0 |
T131 |
4330 |
49 |
0 |
0 |
T134 |
112339 |
806 |
0 |
0 |
T159 |
181252 |
488 |
0 |
0 |
T160 |
13427 |
35 |
0 |
0 |
T161 |
21727 |
55 |
0 |
0 |
T162 |
13391 |
20 |
0 |
0 |
T163 |
14711 |
116 |
0 |
0 |
T166 |
15768 |
1 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
6455 |
0 |
0 |
T115 |
9565 |
75 |
0 |
0 |
T131 |
4330 |
10 |
0 |
0 |
T134 |
112339 |
733 |
0 |
0 |
T159 |
181252 |
444 |
0 |
0 |
T160 |
13427 |
1 |
0 |
0 |
T161 |
21727 |
46 |
0 |
0 |
T162 |
13391 |
35 |
0 |
0 |
T163 |
14711 |
116 |
0 |
0 |
T164 |
6232 |
12 |
0 |
0 |
T166 |
15768 |
4 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
6414 |
0 |
0 |
T99 |
5713 |
7 |
0 |
0 |
T115 |
9565 |
135 |
0 |
0 |
T134 |
112339 |
753 |
0 |
0 |
T159 |
181252 |
460 |
0 |
0 |
T160 |
13427 |
44 |
0 |
0 |
T161 |
21727 |
32 |
0 |
0 |
T162 |
13391 |
33 |
0 |
0 |
T163 |
14711 |
215 |
0 |
0 |
T164 |
6232 |
11 |
0 |
0 |
T165 |
7521 |
139 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
7100 |
0 |
0 |
T115 |
9565 |
53 |
0 |
0 |
T124 |
4051 |
2 |
0 |
0 |
T131 |
4330 |
57 |
0 |
0 |
T134 |
112339 |
822 |
0 |
0 |
T159 |
181252 |
425 |
0 |
0 |
T160 |
13427 |
73 |
0 |
0 |
T161 |
21727 |
49 |
0 |
0 |
T162 |
13391 |
37 |
0 |
0 |
T163 |
14711 |
241 |
0 |
0 |
T164 |
6232 |
136 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
5293 |
0 |
0 |
T115 |
9565 |
143 |
0 |
0 |
T124 |
4051 |
4 |
0 |
0 |
T131 |
4330 |
87 |
0 |
0 |
T134 |
112339 |
729 |
0 |
0 |
T159 |
181252 |
420 |
0 |
0 |
T160 |
13427 |
32 |
0 |
0 |
T161 |
21727 |
37 |
0 |
0 |
T162 |
13391 |
40 |
0 |
0 |
T163 |
14711 |
101 |
0 |
0 |
T164 |
6232 |
135 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3481 |
0 |
0 |
T103 |
14308 |
9 |
0 |
0 |
T115 |
9565 |
12 |
0 |
0 |
T124 |
4051 |
23 |
0 |
0 |
T131 |
4330 |
13 |
0 |
0 |
T134 |
112339 |
680 |
0 |
0 |
T159 |
181252 |
461 |
0 |
0 |
T160 |
13427 |
39 |
0 |
0 |
T161 |
21727 |
66 |
0 |
0 |
T162 |
13391 |
5 |
0 |
0 |
T163 |
14711 |
103 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3507 |
0 |
0 |
T115 |
9565 |
1 |
0 |
0 |
T124 |
4051 |
46 |
0 |
0 |
T131 |
4330 |
38 |
0 |
0 |
T134 |
112339 |
784 |
0 |
0 |
T159 |
181252 |
421 |
0 |
0 |
T160 |
13427 |
51 |
0 |
0 |
T161 |
21727 |
73 |
0 |
0 |
T162 |
13391 |
52 |
0 |
0 |
T163 |
14711 |
103 |
0 |
0 |
T164 |
6232 |
50 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3880 |
0 |
0 |
T111 |
12539 |
3 |
0 |
0 |
T115 |
9565 |
45 |
0 |
0 |
T124 |
4051 |
47 |
0 |
0 |
T131 |
4330 |
14 |
0 |
0 |
T134 |
112339 |
759 |
0 |
0 |
T159 |
181252 |
481 |
0 |
0 |
T160 |
13427 |
44 |
0 |
0 |
T161 |
21727 |
35 |
0 |
0 |
T162 |
13391 |
62 |
0 |
0 |
T163 |
14711 |
69 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3838 |
0 |
0 |
T115 |
9565 |
57 |
0 |
0 |
T124 |
4051 |
5 |
0 |
0 |
T134 |
112339 |
860 |
0 |
0 |
T159 |
181252 |
398 |
0 |
0 |
T160 |
13427 |
41 |
0 |
0 |
T161 |
21727 |
68 |
0 |
0 |
T162 |
13391 |
78 |
0 |
0 |
T163 |
14711 |
83 |
0 |
0 |
T164 |
6232 |
8 |
0 |
0 |
T165 |
7521 |
66 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3677 |
0 |
0 |
T115 |
9565 |
12 |
0 |
0 |
T124 |
4051 |
42 |
0 |
0 |
T131 |
4330 |
13 |
0 |
0 |
T134 |
112339 |
772 |
0 |
0 |
T159 |
181252 |
459 |
0 |
0 |
T160 |
13427 |
53 |
0 |
0 |
T161 |
21727 |
53 |
0 |
0 |
T162 |
13391 |
68 |
0 |
0 |
T163 |
14711 |
27 |
0 |
0 |
T164 |
6232 |
41 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3059 |
0 |
0 |
T102 |
14664 |
3 |
0 |
0 |
T115 |
9565 |
35 |
0 |
0 |
T124 |
4051 |
50 |
0 |
0 |
T134 |
112339 |
697 |
0 |
0 |
T159 |
181252 |
452 |
0 |
0 |
T160 |
13427 |
27 |
0 |
0 |
T161 |
21727 |
109 |
0 |
0 |
T162 |
13391 |
56 |
0 |
0 |
T163 |
14711 |
59 |
0 |
0 |
T164 |
6232 |
1 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3653 |
0 |
0 |
T103 |
14308 |
1 |
0 |
0 |
T115 |
9565 |
11 |
0 |
0 |
T124 |
4051 |
36 |
0 |
0 |
T131 |
4330 |
21 |
0 |
0 |
T134 |
112339 |
793 |
0 |
0 |
T159 |
181252 |
469 |
0 |
0 |
T160 |
13427 |
57 |
0 |
0 |
T161 |
21727 |
73 |
0 |
0 |
T162 |
13391 |
19 |
0 |
0 |
T163 |
14711 |
45 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3284 |
0 |
0 |
T104 |
19496 |
7 |
0 |
0 |
T115 |
9565 |
71 |
0 |
0 |
T124 |
4051 |
2 |
0 |
0 |
T131 |
4330 |
20 |
0 |
0 |
T134 |
112339 |
766 |
0 |
0 |
T159 |
181252 |
412 |
0 |
0 |
T160 |
13427 |
34 |
0 |
0 |
T161 |
21727 |
26 |
0 |
0 |
T162 |
13391 |
21 |
0 |
0 |
T163 |
14711 |
60 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3881 |
0 |
0 |
T106 |
17054 |
3 |
0 |
0 |
T115 |
9565 |
44 |
0 |
0 |
T124 |
4051 |
58 |
0 |
0 |
T134 |
112339 |
778 |
0 |
0 |
T159 |
181252 |
464 |
0 |
0 |
T160 |
13427 |
40 |
0 |
0 |
T161 |
21727 |
37 |
0 |
0 |
T162 |
13391 |
67 |
0 |
0 |
T163 |
14711 |
139 |
0 |
0 |
T166 |
15768 |
7 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3478 |
0 |
0 |
T111 |
12539 |
3 |
0 |
0 |
T115 |
9565 |
66 |
0 |
0 |
T124 |
4051 |
1 |
0 |
0 |
T131 |
4330 |
18 |
0 |
0 |
T134 |
112339 |
761 |
0 |
0 |
T159 |
181252 |
448 |
0 |
0 |
T160 |
13427 |
14 |
0 |
0 |
T161 |
21727 |
45 |
0 |
0 |
T162 |
13391 |
58 |
0 |
0 |
T163 |
14711 |
28 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3807 |
0 |
0 |
T115 |
9565 |
37 |
0 |
0 |
T124 |
4051 |
9 |
0 |
0 |
T131 |
4330 |
4 |
0 |
0 |
T134 |
112339 |
807 |
0 |
0 |
T159 |
181252 |
502 |
0 |
0 |
T160 |
13427 |
11 |
0 |
0 |
T161 |
21727 |
45 |
0 |
0 |
T162 |
13391 |
53 |
0 |
0 |
T163 |
14711 |
93 |
0 |
0 |
T164 |
6232 |
11 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3472 |
0 |
0 |
T104 |
19496 |
5 |
0 |
0 |
T115 |
9565 |
45 |
0 |
0 |
T124 |
4051 |
4 |
0 |
0 |
T131 |
4330 |
1 |
0 |
0 |
T134 |
112339 |
781 |
0 |
0 |
T159 |
181252 |
402 |
0 |
0 |
T160 |
13427 |
94 |
0 |
0 |
T161 |
21727 |
88 |
0 |
0 |
T162 |
13391 |
48 |
0 |
0 |
T163 |
14711 |
59 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3619 |
0 |
0 |
T115 |
9565 |
16 |
0 |
0 |
T124 |
4051 |
48 |
0 |
0 |
T131 |
4330 |
24 |
0 |
0 |
T134 |
112339 |
769 |
0 |
0 |
T159 |
181252 |
485 |
0 |
0 |
T160 |
13427 |
57 |
0 |
0 |
T161 |
21727 |
62 |
0 |
0 |
T162 |
13391 |
26 |
0 |
0 |
T163 |
14711 |
162 |
0 |
0 |
T164 |
6232 |
8 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3593 |
0 |
0 |
T115 |
9565 |
14 |
0 |
0 |
T131 |
4330 |
27 |
0 |
0 |
T134 |
112339 |
701 |
0 |
0 |
T159 |
181252 |
432 |
0 |
0 |
T160 |
13427 |
39 |
0 |
0 |
T161 |
21727 |
80 |
0 |
0 |
T162 |
13391 |
57 |
0 |
0 |
T163 |
14711 |
18 |
0 |
0 |
T164 |
6232 |
48 |
0 |
0 |
T165 |
7521 |
53 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3508 |
0 |
0 |
T102 |
14664 |
11 |
0 |
0 |
T124 |
4051 |
41 |
0 |
0 |
T131 |
4330 |
28 |
0 |
0 |
T134 |
112339 |
742 |
0 |
0 |
T159 |
181252 |
478 |
0 |
0 |
T160 |
13427 |
58 |
0 |
0 |
T161 |
21727 |
67 |
0 |
0 |
T162 |
13391 |
5 |
0 |
0 |
T163 |
14711 |
119 |
0 |
0 |
T164 |
6232 |
32 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
4015 |
0 |
0 |
T115 |
9565 |
63 |
0 |
0 |
T124 |
4051 |
53 |
0 |
0 |
T131 |
4330 |
4 |
0 |
0 |
T134 |
112339 |
779 |
0 |
0 |
T159 |
181252 |
451 |
0 |
0 |
T160 |
13427 |
30 |
0 |
0 |
T161 |
21727 |
81 |
0 |
0 |
T162 |
13391 |
50 |
0 |
0 |
T163 |
14711 |
98 |
0 |
0 |
T166 |
15768 |
1 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3484 |
0 |
0 |
T115 |
9565 |
36 |
0 |
0 |
T124 |
4051 |
42 |
0 |
0 |
T131 |
4330 |
19 |
0 |
0 |
T134 |
112339 |
753 |
0 |
0 |
T159 |
181252 |
452 |
0 |
0 |
T160 |
13427 |
39 |
0 |
0 |
T161 |
21727 |
22 |
0 |
0 |
T162 |
13391 |
24 |
0 |
0 |
T163 |
14711 |
62 |
0 |
0 |
T164 |
6232 |
6 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3288 |
0 |
0 |
T115 |
9565 |
21 |
0 |
0 |
T124 |
4051 |
1 |
0 |
0 |
T134 |
112339 |
771 |
0 |
0 |
T159 |
181252 |
452 |
0 |
0 |
T160 |
13427 |
5 |
0 |
0 |
T161 |
21727 |
45 |
0 |
0 |
T162 |
13391 |
62 |
0 |
0 |
T163 |
14711 |
57 |
0 |
0 |
T164 |
6232 |
75 |
0 |
0 |
T165 |
7521 |
13 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3774 |
0 |
0 |
T115 |
9565 |
58 |
0 |
0 |
T124 |
4051 |
43 |
0 |
0 |
T131 |
4330 |
29 |
0 |
0 |
T134 |
112339 |
675 |
0 |
0 |
T159 |
181252 |
396 |
0 |
0 |
T160 |
13427 |
37 |
0 |
0 |
T161 |
21727 |
80 |
0 |
0 |
T162 |
13391 |
45 |
0 |
0 |
T163 |
14711 |
101 |
0 |
0 |
T164 |
6232 |
49 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3581 |
0 |
0 |
T103 |
14308 |
4 |
0 |
0 |
T115 |
9565 |
12 |
0 |
0 |
T134 |
112339 |
863 |
0 |
0 |
T159 |
181252 |
381 |
0 |
0 |
T160 |
13427 |
32 |
0 |
0 |
T161 |
21727 |
96 |
0 |
0 |
T162 |
13391 |
20 |
0 |
0 |
T163 |
14711 |
53 |
0 |
0 |
T164 |
6232 |
56 |
0 |
0 |
T165 |
7521 |
36 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3509 |
0 |
0 |
T99 |
5713 |
8 |
0 |
0 |
T115 |
9565 |
14 |
0 |
0 |
T124 |
4051 |
5 |
0 |
0 |
T131 |
4330 |
10 |
0 |
0 |
T134 |
112339 |
811 |
0 |
0 |
T159 |
181252 |
464 |
0 |
0 |
T160 |
13427 |
28 |
0 |
0 |
T161 |
21727 |
68 |
0 |
0 |
T162 |
13391 |
12 |
0 |
0 |
T163 |
14711 |
98 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3128 |
0 |
0 |
T102 |
14664 |
6 |
0 |
0 |
T115 |
9565 |
4 |
0 |
0 |
T124 |
4051 |
41 |
0 |
0 |
T131 |
4330 |
28 |
0 |
0 |
T134 |
112339 |
787 |
0 |
0 |
T159 |
181252 |
434 |
0 |
0 |
T160 |
13427 |
16 |
0 |
0 |
T161 |
21727 |
52 |
0 |
0 |
T162 |
13391 |
54 |
0 |
0 |
T163 |
14711 |
41 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3471 |
0 |
0 |
T104 |
19496 |
2 |
0 |
0 |
T115 |
9565 |
20 |
0 |
0 |
T124 |
4051 |
3 |
0 |
0 |
T134 |
112339 |
791 |
0 |
0 |
T159 |
181252 |
452 |
0 |
0 |
T160 |
13427 |
10 |
0 |
0 |
T161 |
21727 |
56 |
0 |
0 |
T162 |
13391 |
41 |
0 |
0 |
T163 |
14711 |
119 |
0 |
0 |
T164 |
6232 |
2 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3458 |
0 |
0 |
T115 |
9565 |
55 |
0 |
0 |
T124 |
4051 |
4 |
0 |
0 |
T131 |
4330 |
29 |
0 |
0 |
T134 |
112339 |
723 |
0 |
0 |
T159 |
181252 |
439 |
0 |
0 |
T160 |
13427 |
22 |
0 |
0 |
T161 |
21727 |
65 |
0 |
0 |
T162 |
13391 |
43 |
0 |
0 |
T163 |
14711 |
65 |
0 |
0 |
T164 |
6232 |
12 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2233 |
0 |
0 |
T115 |
9565 |
15 |
0 |
0 |
T124 |
4051 |
8 |
0 |
0 |
T134 |
112339 |
740 |
0 |
0 |
T159 |
181252 |
464 |
0 |
0 |
T160 |
13427 |
62 |
0 |
0 |
T161 |
21727 |
125 |
0 |
0 |
T162 |
13391 |
24 |
0 |
0 |
T163 |
14711 |
28 |
0 |
0 |
T164 |
6232 |
17 |
0 |
0 |
T165 |
7521 |
7 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2140 |
0 |
0 |
T115 |
9565 |
15 |
0 |
0 |
T131 |
4330 |
9 |
0 |
0 |
T134 |
112339 |
783 |
0 |
0 |
T159 |
181252 |
466 |
0 |
0 |
T160 |
13427 |
41 |
0 |
0 |
T161 |
21727 |
110 |
0 |
0 |
T162 |
13391 |
26 |
0 |
0 |
T163 |
14711 |
18 |
0 |
0 |
T164 |
6232 |
9 |
0 |
0 |
T165 |
7521 |
12 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2094 |
0 |
0 |
T124 |
4051 |
7 |
0 |
0 |
T134 |
112339 |
740 |
0 |
0 |
T159 |
181252 |
472 |
0 |
0 |
T160 |
13427 |
47 |
0 |
0 |
T161 |
21727 |
56 |
0 |
0 |
T162 |
13391 |
42 |
0 |
0 |
T163 |
14711 |
17 |
0 |
0 |
T164 |
6232 |
6 |
0 |
0 |
T165 |
7521 |
24 |
0 |
0 |
T167 |
35540 |
53 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2050 |
0 |
0 |
T115 |
9565 |
16 |
0 |
0 |
T124 |
4051 |
3 |
0 |
0 |
T131 |
4330 |
4 |
0 |
0 |
T134 |
112339 |
766 |
0 |
0 |
T159 |
181252 |
479 |
0 |
0 |
T160 |
13427 |
29 |
0 |
0 |
T161 |
21727 |
66 |
0 |
0 |
T162 |
13391 |
17 |
0 |
0 |
T163 |
14711 |
23 |
0 |
0 |
T164 |
6232 |
16 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2478 |
0 |
0 |
T115 |
9565 |
31 |
0 |
0 |
T124 |
4051 |
2 |
0 |
0 |
T134 |
112339 |
750 |
0 |
0 |
T159 |
181252 |
465 |
0 |
0 |
T160 |
13427 |
74 |
0 |
0 |
T161 |
21727 |
64 |
0 |
0 |
T162 |
13391 |
55 |
0 |
0 |
T163 |
14711 |
23 |
0 |
0 |
T164 |
6232 |
20 |
0 |
0 |
T165 |
7521 |
23 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
3954 |
0 |
0 |
T11 |
364389 |
14 |
0 |
0 |
T12 |
645326 |
0 |
0 |
0 |
T13 |
140134 |
37 |
0 |
0 |
T16 |
0 |
21 |
0 |
0 |
T19 |
0 |
10 |
0 |
0 |
T22 |
2126 |
0 |
0 |
0 |
T23 |
71569 |
0 |
0 |
0 |
T24 |
232262 |
0 |
0 |
0 |
T25 |
405298 |
0 |
0 |
0 |
T26 |
1612 |
0 |
0 |
0 |
T27 |
41202 |
0 |
0 |
0 |
T28 |
333258 |
0 |
0 |
0 |
T78 |
0 |
29 |
0 |
0 |
T168 |
0 |
24 |
0 |
0 |
T169 |
0 |
41 |
0 |
0 |
T170 |
0 |
36 |
0 |
0 |
T171 |
0 |
21 |
0 |
0 |
T172 |
0 |
16 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2164 |
0 |
0 |
T104 |
19496 |
10 |
0 |
0 |
T115 |
9565 |
1 |
0 |
0 |
T134 |
112339 |
812 |
0 |
0 |
T159 |
181252 |
469 |
0 |
0 |
T160 |
13427 |
56 |
0 |
0 |
T161 |
21727 |
68 |
0 |
0 |
T162 |
13391 |
49 |
0 |
0 |
T163 |
14711 |
23 |
0 |
0 |
T164 |
6232 |
7 |
0 |
0 |
T165 |
7521 |
13 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2245 |
0 |
0 |
T104 |
19496 |
2 |
0 |
0 |
T124 |
4051 |
10 |
0 |
0 |
T131 |
4330 |
1 |
0 |
0 |
T134 |
112339 |
767 |
0 |
0 |
T159 |
181252 |
480 |
0 |
0 |
T160 |
13427 |
60 |
0 |
0 |
T161 |
21727 |
99 |
0 |
0 |
T162 |
13391 |
86 |
0 |
0 |
T163 |
14711 |
26 |
0 |
0 |
T164 |
6232 |
17 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1935 |
0 |
0 |
T104 |
19496 |
14 |
0 |
0 |
T124 |
4051 |
1 |
0 |
0 |
T134 |
112339 |
770 |
0 |
0 |
T159 |
181252 |
457 |
0 |
0 |
T160 |
13427 |
86 |
0 |
0 |
T161 |
21727 |
46 |
0 |
0 |
T162 |
13391 |
25 |
0 |
0 |
T163 |
14711 |
10 |
0 |
0 |
T164 |
6232 |
13 |
0 |
0 |
T165 |
7521 |
7 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2079 |
0 |
0 |
T104 |
19496 |
6 |
0 |
0 |
T115 |
9565 |
1 |
0 |
0 |
T124 |
4051 |
5 |
0 |
0 |
T134 |
112339 |
808 |
0 |
0 |
T159 |
181252 |
440 |
0 |
0 |
T160 |
13427 |
66 |
0 |
0 |
T161 |
21727 |
134 |
0 |
0 |
T162 |
13391 |
87 |
0 |
0 |
T163 |
14711 |
29 |
0 |
0 |
T164 |
6232 |
11 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1817 |
0 |
0 |
T124 |
4051 |
9 |
0 |
0 |
T134 |
112339 |
737 |
0 |
0 |
T159 |
181252 |
439 |
0 |
0 |
T160 |
13427 |
38 |
0 |
0 |
T161 |
21727 |
31 |
0 |
0 |
T162 |
13391 |
26 |
0 |
0 |
T163 |
14711 |
33 |
0 |
0 |
T164 |
6232 |
5 |
0 |
0 |
T167 |
35540 |
37 |
0 |
0 |
T173 |
6379 |
21 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1906 |
0 |
0 |
T115 |
9565 |
14 |
0 |
0 |
T124 |
4051 |
4 |
0 |
0 |
T134 |
112339 |
686 |
0 |
0 |
T159 |
181252 |
438 |
0 |
0 |
T160 |
13427 |
18 |
0 |
0 |
T161 |
21727 |
96 |
0 |
0 |
T162 |
13391 |
66 |
0 |
0 |
T163 |
14711 |
15 |
0 |
0 |
T164 |
6232 |
2 |
0 |
0 |
T165 |
7521 |
11 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2320 |
0 |
0 |
T115 |
9565 |
25 |
0 |
0 |
T124 |
4051 |
7 |
0 |
0 |
T134 |
112339 |
751 |
0 |
0 |
T159 |
181252 |
478 |
0 |
0 |
T160 |
13427 |
31 |
0 |
0 |
T161 |
21727 |
52 |
0 |
0 |
T162 |
13391 |
16 |
0 |
0 |
T163 |
14711 |
42 |
0 |
0 |
T164 |
6232 |
19 |
0 |
0 |
T165 |
7521 |
13 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1967 |
0 |
0 |
T115 |
9565 |
7 |
0 |
0 |
T134 |
112339 |
759 |
0 |
0 |
T159 |
181252 |
486 |
0 |
0 |
T160 |
13427 |
42 |
0 |
0 |
T161 |
21727 |
72 |
0 |
0 |
T162 |
13391 |
10 |
0 |
0 |
T163 |
14711 |
28 |
0 |
0 |
T164 |
6232 |
3 |
0 |
0 |
T165 |
7521 |
9 |
0 |
0 |
T167 |
35540 |
29 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2544 |
0 |
0 |
T115 |
9565 |
30 |
0 |
0 |
T124 |
4051 |
14 |
0 |
0 |
T134 |
112339 |
724 |
0 |
0 |
T159 |
181252 |
463 |
0 |
0 |
T160 |
13427 |
44 |
0 |
0 |
T161 |
21727 |
96 |
0 |
0 |
T162 |
13391 |
15 |
0 |
0 |
T163 |
14711 |
74 |
0 |
0 |
T164 |
6232 |
21 |
0 |
0 |
T165 |
7521 |
45 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2127 |
0 |
0 |
T124 |
4051 |
1 |
0 |
0 |
T131 |
4330 |
5 |
0 |
0 |
T134 |
112339 |
754 |
0 |
0 |
T159 |
181252 |
457 |
0 |
0 |
T160 |
13427 |
87 |
0 |
0 |
T161 |
21727 |
75 |
0 |
0 |
T162 |
13391 |
15 |
0 |
0 |
T163 |
14711 |
21 |
0 |
0 |
T164 |
6232 |
13 |
0 |
0 |
T165 |
7521 |
15 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2012 |
0 |
0 |
T115 |
9565 |
11 |
0 |
0 |
T124 |
4051 |
6 |
0 |
0 |
T131 |
4330 |
9 |
0 |
0 |
T134 |
112339 |
795 |
0 |
0 |
T159 |
181252 |
427 |
0 |
0 |
T160 |
13427 |
50 |
0 |
0 |
T161 |
21727 |
64 |
0 |
0 |
T162 |
13391 |
40 |
0 |
0 |
T163 |
14711 |
21 |
0 |
0 |
T164 |
6232 |
7 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1903 |
0 |
0 |
T104 |
19496 |
5 |
0 |
0 |
T115 |
9565 |
22 |
0 |
0 |
T124 |
4051 |
7 |
0 |
0 |
T134 |
112339 |
815 |
0 |
0 |
T159 |
181252 |
414 |
0 |
0 |
T160 |
13427 |
11 |
0 |
0 |
T161 |
21727 |
43 |
0 |
0 |
T162 |
13391 |
25 |
0 |
0 |
T163 |
14711 |
24 |
0 |
0 |
T164 |
6232 |
5 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
2123 |
0 |
0 |
T115 |
9565 |
13 |
0 |
0 |
T124 |
4051 |
9 |
0 |
0 |
T131 |
4330 |
5 |
0 |
0 |
T134 |
112339 |
807 |
0 |
0 |
T159 |
181252 |
444 |
0 |
0 |
T160 |
13427 |
69 |
0 |
0 |
T161 |
21727 |
104 |
0 |
0 |
T162 |
13391 |
61 |
0 |
0 |
T163 |
14711 |
28 |
0 |
0 |
T164 |
6232 |
5 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1945 |
0 |
0 |
T115 |
9565 |
1 |
0 |
0 |
T124 |
4051 |
5 |
0 |
0 |
T131 |
4330 |
5 |
0 |
0 |
T134 |
112339 |
776 |
0 |
0 |
T159 |
181252 |
416 |
0 |
0 |
T160 |
13427 |
28 |
0 |
0 |
T161 |
21727 |
114 |
0 |
0 |
T162 |
13391 |
53 |
0 |
0 |
T163 |
14711 |
35 |
0 |
0 |
T164 |
6232 |
2 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1958 |
0 |
0 |
T115 |
9565 |
31 |
0 |
0 |
T124 |
4051 |
10 |
0 |
0 |
T134 |
112339 |
714 |
0 |
0 |
T159 |
181252 |
500 |
0 |
0 |
T160 |
13427 |
41 |
0 |
0 |
T161 |
21727 |
37 |
0 |
0 |
T162 |
13391 |
75 |
0 |
0 |
T163 |
14711 |
24 |
0 |
0 |
T164 |
6232 |
15 |
0 |
0 |
T165 |
7521 |
7 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454345317 |
1922 |
0 |
0 |
T106 |
17054 |
5 |
0 |
0 |
T115 |
9565 |
3 |
0 |
0 |
T124 |
4051 |
5 |
0 |
0 |
T134 |
112339 |
764 |
0 |
0 |
T159 |
181252 |
458 |
0 |
0 |
T160 |
13427 |
23 |
0 |
0 |
T161 |
21727 |
49 |
0 |
0 |
T162 |
13391 |
25 |
0 |
0 |
T163 |
14711 |
15 |
0 |
0 |
T164 |
6232 |
6 |
0 |
0 |