Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3583422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4311873

1

T1

899

T2

1892

T3

1316

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4226101	1			T1	8		T2	285		T3	688
values[0x0]	1833510	1			T1	428		T2	849		T3	441
values[0x1]	1835684	1			T1	469		T2	910		T3	463

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2533408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5361887

1

T1

902

T2

1931

T3

1384

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31313	1			T2	7		T3	6		T5	8
valid_sources[0x01]	28813	1			T2	11		T3	10		T5	23
valid_sources[0x02]	28810	1			T2	4		T3	2		T5	5
valid_sources[0x03]	28666	1			T2	4		T3	6		T5	17
valid_sources[0x04]	27843	1			T1	8		T2	2		T3	15
valid_sources[0x05]	35649	1			T2	2		T3	7		T5	15
valid_sources[0x06]	33901	1			T2	8		T3	3		T5	15
valid_sources[0x07]	30282	1			T2	18		T3	7		T5	7
valid_sources[0x08]	30123	1			T1	11		T2	13		T3	9
valid_sources[0x09]	30738	1			T3	9		T8	8		T11	2
valid_sources[0x0a]	30624	1			T2	6		T3	5		T5	25
valid_sources[0x0b]	31669	1			T1	1		T2	2		T3	10
valid_sources[0x0c]	29282	1			T2	8		T3	3		T5	8
valid_sources[0x0d]	28719	1			T1	2		T2	6		T3	6
valid_sources[0x0e]	30554	1			T1	3		T2	25		T3	12
valid_sources[0x0f]	30183	1			T2	4		T3	5		T5	4
valid_sources[0x10]	32742	1			T1	3		T2	6		T3	2
valid_sources[0x11]	30895	1			T2	5		T3	2		T5	29
valid_sources[0x12]	32515	1			T2	5		T3	1		T5	20
valid_sources[0x13]	60545	1			T1	5		T2	10		T3	4
valid_sources[0x14]	31229	1			T1	11		T2	10		T3	6
valid_sources[0x15]	28384	1			T1	6		T2	11		T3	3
valid_sources[0x16]	33449	1			T1	4		T2	8		T3	6
valid_sources[0x17]	29318	1			T1	3		T2	7		T3	2
valid_sources[0x18]	31122	1			T2	5		T3	3		T5	21
valid_sources[0x19]	29890	1			T2	6		T3	2		T5	18
valid_sources[0x1a]	27918	1			T1	4		T2	4		T3	1
valid_sources[0x1b]	32142	1			T1	7		T2	13		T3	10
valid_sources[0x1c]	32031	1			T2	19		T3	3		T5	17
valid_sources[0x1d]	34321	1			T2	7		T5	6		T8	2
valid_sources[0x1e]	30912	1			T1	3		T2	9		T3	12
valid_sources[0x1f]	31471	1			T1	5		T2	11		T3	8
valid_sources[0x20]	30423	1			T1	7		T2	2		T3	4
valid_sources[0x21]	28859	1			T2	4		T3	1		T5	1
valid_sources[0x22]	29782	1			T1	19		T2	6		T3	4
valid_sources[0x23]	28024	1			T1	7		T2	10		T3	2
valid_sources[0x24]	29808	1			T1	1		T2	12		T3	10
valid_sources[0x25]	28915	1			T1	7		T2	8		T3	5
valid_sources[0x26]	30609	1			T2	20		T3	3		T5	13
valid_sources[0x27]	31856	1			T2	9		T3	7		T5	4
valid_sources[0x28]	30110	1			T1	6		T2	3		T3	7
valid_sources[0x29]	57143	1			T2	13		T5	14		T7	1
valid_sources[0x2a]	32400	1			T2	12		T3	4		T5	7
valid_sources[0x2b]	30672	1			T1	3		T3	7		T5	10
valid_sources[0x2c]	27179	1			T2	10		T3	8		T5	8
valid_sources[0x2d]	32236	1			T1	8		T2	8		T3	14
valid_sources[0x2e]	30410	1			T2	9		T3	4		T5	4
valid_sources[0x2f]	28639	1			T1	1		T2	6		T3	2
valid_sources[0x30]	31092	1			T1	8		T2	4		T3	14
valid_sources[0x31]	30947	1			T1	14		T2	11		T3	3
valid_sources[0x32]	33728	1			T1	3		T2	9		T3	10
valid_sources[0x33]	32647	1			T2	15		T3	7		T5	6
valid_sources[0x34]	28239	1			T2	21		T3	6		T5	22
valid_sources[0x35]	27057	1			T2	13		T3	5		T5	7
valid_sources[0x36]	30389	1			T2	3		T3	3		T5	8
valid_sources[0x37]	32976	1			T1	6		T2	1		T3	12
valid_sources[0x38]	30163	1			T1	4		T2	9		T3	1
valid_sources[0x39]	29422	1			T1	10		T2	11		T3	6
valid_sources[0x3a]	31154	1			T1	18		T2	6		T3	5
valid_sources[0x3b]	36133	1			T2	5		T3	17		T5	3
valid_sources[0x3c]	30803	1			T2	18		T3	2		T5	13
valid_sources[0x3d]	29040	1			T1	3		T2	9		T3	3
valid_sources[0x3e]	30553	1			T2	18		T3	7		T5	13
valid_sources[0x3f]	30000	1			T1	5		T2	3		T3	4
valid_sources[0x40]	33348	1			T2	6		T3	7		T5	19
valid_sources[0x41]	31786	1			T2	2		T3	10		T5	4
valid_sources[0x42]	30888	1			T2	9		T3	4		T5	10
valid_sources[0x43]	29045	1			T1	3		T2	1		T3	4
valid_sources[0x44]	28169	1			T2	14		T3	8		T5	9
valid_sources[0x45]	28740	1			T2	7		T3	6		T5	4
valid_sources[0x46]	29783	1			T2	1		T3	8		T5	6
valid_sources[0x47]	30675	1			T1	1		T2	9		T3	10
valid_sources[0x48]	29817	1			T1	1		T2	6		T3	7
valid_sources[0x49]	34416	1			T1	9		T2	5		T3	5
valid_sources[0x4a]	28754	1			T1	3		T2	3		T3	2
valid_sources[0x4b]	30698	1			T2	4		T3	1		T5	5
valid_sources[0x4c]	30143	1			T1	4		T2	16		T3	11
valid_sources[0x4d]	26580	1			T1	11		T2	7		T3	6
valid_sources[0x4e]	29205	1			T2	10		T3	2		T5	19
valid_sources[0x4f]	28669	1			T2	6		T3	19		T5	9
valid_sources[0x50]	27731	1			T2	10		T3	10		T5	10
valid_sources[0x51]	29102	1			T3	9		T5	5		T7	8
valid_sources[0x52]	31282	1			T1	2		T2	2		T3	9
valid_sources[0x53]	28903	1			T1	5		T2	10		T3	1
valid_sources[0x54]	27840	1			T1	11		T2	9		T3	7
valid_sources[0x55]	32449	1			T1	11		T2	12		T3	13
valid_sources[0x56]	30770	1			T1	2		T2	3		T3	5
valid_sources[0x57]	29656	1			T2	5		T3	8		T5	11
valid_sources[0x58]	31319	1			T1	4		T2	12		T3	12
valid_sources[0x59]	29656	1			T2	9		T3	4		T5	30
valid_sources[0x5a]	30194	1			T2	14		T3	6		T5	7
valid_sources[0x5b]	30383	1			T2	1		T3	15		T5	6
valid_sources[0x5c]	30417	1			T1	4		T2	20		T3	5
valid_sources[0x5d]	29792	1			T1	16		T2	2		T3	10
valid_sources[0x5e]	31878	1			T1	6		T2	12		T3	12
valid_sources[0x5f]	29175	1			T1	7		T2	10		T3	3
valid_sources[0x60]	27649	1			T1	7		T2	12		T3	5
valid_sources[0x61]	29703	1			T1	1		T3	6		T5	7
valid_sources[0x62]	26988	1			T2	5		T3	8		T5	10
valid_sources[0x63]	27036	1			T2	14		T3	7		T5	1
valid_sources[0x64]	32201	1			T1	1		T2	7		T3	8
valid_sources[0x65]	28984	1			T2	11		T3	4		T5	9
valid_sources[0x66]	26240	1			T2	4		T3	7		T5	19
valid_sources[0x67]	29925	1			T2	4		T3	3		T5	4
valid_sources[0x68]	29276	1			T1	4		T2	28		T3	5
valid_sources[0x69]	31539	1			T1	6		T2	9		T3	4
valid_sources[0x6a]	29084	1			T1	1		T2	15		T3	1
valid_sources[0x6b]	31119	1			T2	13		T3	4		T5	8
valid_sources[0x6c]	30727	1			T2	7		T3	7		T5	1
valid_sources[0x6d]	28264	1			T2	6		T3	4		T5	1
valid_sources[0x6e]	29484	1			T1	8		T2	7		T3	6
valid_sources[0x6f]	31185	1			T1	7		T2	8		T3	3
valid_sources[0x70]	30367	1			T1	22		T2	15		T3	7
valid_sources[0x71]	28769	1			T1	2		T2	5		T3	9
valid_sources[0x72]	29775	1			T1	8		T2	8		T3	4
valid_sources[0x73]	28232	1			T2	3		T3	12		T5	6
valid_sources[0x74]	30015	1			T1	9		T2	18		T3	2
valid_sources[0x75]	27233	1			T2	3		T3	6		T5	5
valid_sources[0x76]	29594	1			T1	7		T2	17		T3	3
valid_sources[0x77]	27665	1			T1	12		T3	3		T5	8
valid_sources[0x78]	29833	1			T1	4		T2	2		T3	12
valid_sources[0x79]	30759	1			T2	2		T3	1		T5	16
valid_sources[0x7a]	29084	1			T1	3		T2	2		T3	4
valid_sources[0x7b]	30749	1			T1	5		T2	5		T3	11
valid_sources[0x7c]	28688	1			T1	3		T2	7		T3	14
valid_sources[0x7d]	27250	1			T1	2		T3	14		T5	13
valid_sources[0x7e]	27832	1			T2	2		T3	11		T5	19
valid_sources[0x7f]	31581	1			T1	6		T2	1		T3	6
valid_sources[0x80]	30722	1			T3	5		T5	7		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

979849

1

T1

4

T2

140

T3

418

values[0x0]

all_enables

biggest_size

1677600

1

T1

428

T2

848

T3

440

values[0x1]

all_enables

biggest_size

1654424

1

T1

467

T2

904

T3

458