Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3597976

1

T1

6

T2

152

T3

276

full_word

4310678

1

T1

899

T2

1892

T3

1316

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7908194	1			T1	905		T2	2044		T3	1592
auto[TlIntgErrCmd]	150	1			T98	10		T102	3		T103	10
auto[TlIntgErrData]	144	1			T98	12		T102	6		T103	10
auto[TlIntgErrBoth]	166	1			T98	8		T102	1		T103	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4226959

1

T1

8

T2

285

T3

688

auto[1]

3681695

1

T1

897

T2

1759

T3

904

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3246863	1			T1	4		T2	145		T3	270
auto[TlIntgErrNone]	partial	auto[1]	350693	1			T1	2		T2	7		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	979899	1			T1	4		T2	140		T3	418
auto[TlIntgErrNone]	full_word	auto[1]	3330739	1			T1	895		T2	1752		T3	898
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T98	4		T103	3		T174	1
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T98	6		T102	3		T103	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T170	1		T175	1		T176	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T177	1		T174	1		T170	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T98	3		T102	3		T103	4
auto[TlIntgErrData]	partial	auto[1]	66	1			T98	6		T102	2		T103	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T102	1		T178	1		T179	2
auto[TlIntgErrData]	full_word	auto[1]	10	1			T98	3		T174	1		T169	1
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T98	2		T103	4		T177	3
auto[TlIntgErrBoth]	partial	auto[1]	86	1			T98	4		T102	1		T103	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T98	1		T169	1		T180	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T98	1		T174	1		T170	1