Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461077714	3042526	0	0
DepthKnown_A	461077714	460939414	0	0
RvalidKnown_A	461077714	460939414	0	0
WreadyKnown_A	461077714	460939414	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	3042526	0	0
T1	31338	1663	0	0
T2	161267	2504	0	0
T3	386430	832	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	1663	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	100	0	0
T10	23035	0	0	0
T12	0	10825	0	0
T13	0	9149	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461077714	3351278	0	0
DepthKnown_A	461077714	460939414	0	0
RvalidKnown_A	461077714	460939414	0	0
WreadyKnown_A	461077714	460939414	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	3351278	0	0
T1	31338	832	0	0
T2	161267	4654	0	0
T3	386430	832	0	0
T4	685461	832	0	0
T5	107023	3726	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	511	0	0
T10	23035	0	0	0
T12	0	22024	0	0
T13	0	6656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461077714	193333	0	0
DepthKnown_A	461077714	460939414	0	0
RvalidKnown_A	461077714	460939414	0	0
WreadyKnown_A	461077714	460939414	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	193333	0	0
T3	386430	128	0	0
T4	685461	0	0	0
T5	107023	0	0	0
T6	44268	0	0	0
T7	130998	0	0	0
T8	148096	0	0	0
T9	3199	100	0	0
T10	23035	114	0	0
T11	295815	0	0	0
T12	0	202	0	0
T13	0	352	0	0
T14	0	128	0	0
T15	0	32	0	0
T25	0	1516	0	0
T26	0	746	0	0
T29	0	37	0	0
T46	1396	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461077714	440123	0	0
DepthKnown_A	461077714	460939414	0	0
RvalidKnown_A	461077714	460939414	0	0
WreadyKnown_A	461077714	460939414	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	440123	0	0
T3	386430	128	0	0
T4	685461	0	0	0
T5	107023	0	0	0
T6	44268	0	0	0
T7	130998	0	0	0
T8	148096	0	0	0
T9	3199	484	0	0
T10	23035	505	0	0
T11	295815	0	0	0
T12	0	909	0	0
T13	0	352	0	0
T14	0	523	0	0
T15	0	104	0	0
T25	0	4661	0	0
T26	0	746	0	0
T29	0	37	0	0
T46	1396	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461077714	6161483	0	0
DepthKnown_A	461077714	460939414	0	0
RvalidKnown_A	461077714	460939414	0	0
WreadyKnown_A	461077714	460939414	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	6161483	0	0
T1	31338	73	0	0
T2	161267	383	0	0
T3	386430	632	0	0
T4	685461	22750	0	0
T5	107023	1632	0	0
T6	44268	1425	0	0
T7	130998	535	0	0
T8	148096	282	0	0
T9	3199	1	0	0
T10	23035	765	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461077714	13251668	0	0
DepthKnown_A	461077714	460939414	0	0
RvalidKnown_A	461077714	460939414	0	0
WreadyKnown_A	461077714	460939414	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	13251668	0	0
T1	31338	73	0	0
T2	161267	1717	0	0
T3	386430	632	0	0
T4	685461	22750	0	0
T5	107023	7122	0	0
T6	44268	1425	0	0
T7	130998	1629	0	0
T8	148096	280	0	0
T9	3199	7	0	0
T10	23035	3260	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461077714	460939414	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0