Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T29,T25
1	0	Covered	T10,T29,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T11
1	0	Unreachable
1	1	Covered	T10,T29,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T3,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	769738702	612669129	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	769738702	3944424	0	0
GntImpliesValid_A	769738702	3944424	0	0
GrantKnown_A	769738702	612669129	0	0
IdxKnown_A	769738702	612669129	0	0
IndexIsCorrect_A	769738702	3944424	0	0
LockArbDecision_A	769738702	0	0	0
NoReadyValidNoGrant_A	769738702	0	0	0
ReadyAndValidImplyGrant_A	769738702	3944424	0	0
ReqAndReadyImplyGrant_A	769738702	3944424	0	0
ReqImpliesValid_A	769738702	3944424	0	0
ReqStaysHighUntilGranted0_M	769738702	0	0	0
RoundRobin_A	769738702	7	0	976
ValidKnown_A	769738702	612669129	0	0
gen_data_port_assertion.DataFlow_A	769738702	3944424	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	612669129	0	0
T1	144108	144002	0	0
T2	297861	296721	0	0
T3	481980	481088	0	0
T4	821518	820822	0	0
T5	318275	318266	0	0
T6	64693	64629	0	0
T7	369354	245182	0	0
T8	436496	292215	0	0
T9	3199	3109	0	0
T10	101859	61576	0	0
T11	195252	91752	0	0
T12	393231	391038	0	0
T13	526073	524347	0	0
T14	380312	379328	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	3944424	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	481980	1484	0	0
T4	821518	832	0	0
T5	318275	832	0	0
T6	64693	832	0	0
T7	250176	0	0	0
T8	292296	832	0	0
T9	3199	200	0	0
T10	101859	920	0	0
T11	195252	0	0	0
T12	786462	8788	0	0
T13	526073	7635	0	0
T14	380312	1287	0	0
T16	0	16688	0	0
T18	0	12635	0	0
T25	0	10979	0	0
T26	0	4632	0	0
T29	4464	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	3944424	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	481980	1484	0	0
T4	821518	832	0	0
T5	318275	832	0	0
T6	64693	832	0	0
T7	250176	0	0	0
T8	292296	832	0	0
T9	3199	200	0	0
T10	101859	920	0	0
T11	195252	0	0	0
T12	786462	8788	0	0
T13	526073	7635	0	0
T14	380312	1287	0	0
T16	0	16688	0	0
T18	0	12635	0	0
T25	0	10979	0	0
T26	0	4632	0	0
T29	4464	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	612669129	0	0
T1	144108	144002	0	0
T2	297861	296721	0	0
T3	481980	481088	0	0
T4	821518	820822	0	0
T5	318275	318266	0	0
T6	64693	64629	0	0
T7	369354	245182	0	0
T8	436496	292215	0	0
T9	3199	3109	0	0
T10	101859	61576	0	0
T11	195252	91752	0	0
T12	393231	391038	0	0
T13	526073	524347	0	0
T14	380312	379328	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	612669129	0	0
T1	144108	144002	0	0
T2	297861	296721	0	0
T3	481980	481088	0	0
T4	821518	820822	0	0
T5	318275	318266	0	0
T6	64693	64629	0	0
T7	369354	245182	0	0
T8	436496	292215	0	0
T9	3199	3109	0	0
T10	101859	61576	0	0
T11	195252	91752	0	0
T12	393231	391038	0	0
T13	526073	524347	0	0
T14	380312	379328	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	3944424	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	481980	1484	0	0
T4	821518	832	0	0
T5	318275	832	0	0
T6	64693	832	0	0
T7	250176	0	0	0
T8	292296	832	0	0
T9	3199	200	0	0
T10	101859	920	0	0
T11	195252	0	0	0
T12	786462	8788	0	0
T13	526073	7635	0	0
T14	380312	1287	0	0
T16	0	16688	0	0
T18	0	12635	0	0
T25	0	10979	0	0
T26	0	4632	0	0
T29	4464	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	3944424	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	481980	1484	0	0
T4	821518	832	0	0
T5	318275	832	0	0
T6	64693	832	0	0
T7	250176	0	0	0
T8	292296	832	0	0
T9	3199	200	0	0
T10	101859	920	0	0
T11	195252	0	0	0
T12	786462	8788	0	0
T13	526073	7635	0	0
T14	380312	1287	0	0
T16	0	16688	0	0
T18	0	12635	0	0
T25	0	10979	0	0
T26	0	4632	0	0
T29	4464	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	3944424	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	481980	1484	0	0
T4	821518	832	0	0
T5	318275	832	0	0
T6	64693	832	0	0
T7	250176	0	0	0
T8	292296	832	0	0
T9	3199	200	0	0
T10	101859	920	0	0
T11	195252	0	0	0
T12	786462	8788	0	0
T13	526073	7635	0	0
T14	380312	1287	0	0
T16	0	16688	0	0
T18	0	12635	0	0
T25	0	10979	0	0
T26	0	4632	0	0
T29	4464	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	3944424	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	481980	1484	0	0
T4	821518	832	0	0
T5	318275	832	0	0
T6	64693	832	0	0
T7	250176	0	0	0
T8	292296	832	0	0
T9	3199	200	0	0
T10	101859	920	0	0
T11	195252	0	0	0
T12	786462	8788	0	0
T13	526073	7635	0	0
T14	380312	1287	0	0
T16	0	16688	0	0
T18	0	12635	0	0
T25	0	10979	0	0
T26	0	4632	0	0
T29	4464	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	7	0	976
T25	247368	1	0	1
T26	475879	0	0	1
T27	710890	0	0	1
T28	1122	0	0	1
T38	467702	0	0	1
T39	20425	0	0	1
T40	15179	0	0	1
T43	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	66161	0	0	1
T68	28756	0	0	1
T69	1908	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	612669129	0	0
T1	144108	144002	0	0
T2	297861	296721	0	0
T3	481980	481088	0	0
T4	821518	820822	0	0
T5	318275	318266	0	0
T6	64693	64629	0	0
T7	369354	245182	0	0
T8	436496	292215	0	0
T9	3199	3109	0	0
T10	101859	61576	0	0
T11	195252	91752	0	0
T12	393231	391038	0	0
T13	526073	524347	0	0
T14	380312	379328	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769738702	3944424	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	481980	1484	0	0
T4	821518	832	0	0
T5	318275	832	0	0
T6	64693	832	0	0
T7	250176	0	0	0
T8	292296	832	0	0
T9	3199	200	0	0
T10	101859	920	0	0
T11	195252	0	0	0
T12	786462	8788	0	0
T13	526073	7635	0	0
T14	380312	1287	0	0
T16	0	16688	0	0
T18	0	12635	0	0
T25	0	10979	0	0
T26	0	4632	0	0
T29	4464	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T29,T25
1	0	Covered	T10,T29,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T11
1	0	Unreachable
1	1	Covered	T10,T29,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T29,T25
0	0	1	Unreachable
0	0	0	Covered	T7,T10,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T29,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T29,T25
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	155559915	28230080	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	155559915	634212	0	0
GntImpliesValid_A	155559915	634212	0	0
GrantKnown_A	155559915	28230080	0	0
IdxKnown_A	155559915	28230080	0	0
IndexIsCorrect_A	155559915	634212	0	0
LockArbDecision_A	155559915	0	0	0
NoReadyValidNoGrant_A	155559915	0	0	0
ReadyAndValidImplyGrant_A	155559915	634212	0	0
ReqAndReadyImplyGrant_A	155559915	634212	0	0
ReqImpliesValid_A	155559915	634212	0	0
ReqStaysHighUntilGranted0_M	155559915	0	0	0
RoundRobin_A	155559915	0	0	0
ValidKnown_A	155559915	28230080	0	0
gen_data_port_assertion.DataFlow_A	155559915	634212	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	28230080	0	0
T7	119178	114280	0	0
T8	144200	0	0	0
T10	39412	38624	0	0
T11	97626	91752	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	634212	0	0
T10	39412	635	0	0
T11	97626	0	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T16	0	5928	0	0
T18	0	6008	0	0
T25	0	5705	0	0
T26	0	4632	0	0
T29	2232	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	634212	0	0
T10	39412	635	0	0
T11	97626	0	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T16	0	5928	0	0
T18	0	6008	0	0
T25	0	5705	0	0
T26	0	4632	0	0
T29	2232	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	28230080	0	0
T7	119178	114280	0	0
T8	144200	0	0	0
T10	39412	38624	0	0
T11	97626	91752	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	28230080	0	0
T7	119178	114280	0	0
T8	144200	0	0	0
T10	39412	38624	0	0
T11	97626	91752	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	634212	0	0
T10	39412	635	0	0
T11	97626	0	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T16	0	5928	0	0
T18	0	6008	0	0
T25	0	5705	0	0
T26	0	4632	0	0
T29	2232	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	634212	0	0
T10	39412	635	0	0
T11	97626	0	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T16	0	5928	0	0
T18	0	6008	0	0
T25	0	5705	0	0
T26	0	4632	0	0
T29	2232	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	634212	0	0
T10	39412	635	0	0
T11	97626	0	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T16	0	5928	0	0
T18	0	6008	0	0
T25	0	5705	0	0
T26	0	4632	0	0
T29	2232	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	634212	0	0
T10	39412	635	0	0
T11	97626	0	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T16	0	5928	0	0
T18	0	6008	0	0
T25	0	5705	0	0
T26	0	4632	0	0
T29	2232	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	28230080	0	0
T7	119178	114280	0	0
T8	144200	0	0	0
T10	39412	38624	0	0
T11	97626	91752	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T23	0	576	0	0
T24	0	288	0	0
T29	2232	2232	0	0
T30	750	648	0	0
T31	504	504	0	0
T33	0	86696	0	0
T35	0	576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	634212	0	0
T10	39412	635	0	0
T11	97626	0	0	0
T12	393231	0	0	0
T13	526073	0	0	0
T14	380312	0	0	0
T16	0	5928	0	0
T18	0	6008	0	0
T25	0	5705	0	0
T26	0	4632	0	0
T29	2232	162	0	0
T30	750	0	0	0
T31	504	0	0	0
T33	92237	0	0	0
T38	0	5700	0	0
T48	16596	0	0	0
T60	0	183	0	0
T61	0	467	0	0
T62	0	4850	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T3,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	155559915	125909200	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	155559915	936686	0	0
GntImpliesValid_A	155559915	936686	0	0
GrantKnown_A	155559915	125909200	0	0
IdxKnown_A	155559915	125909200	0	0
IndexIsCorrect_A	155559915	936686	0	0
LockArbDecision_A	155559915	0	0	0
NoReadyValidNoGrant_A	155559915	0	0	0
ReadyAndValidImplyGrant_A	155559915	936686	0	0
ReqAndReadyImplyGrant_A	155559915	936686	0	0
ReqImpliesValid_A	155559915	936686	0	0
ReqStaysHighUntilGranted0_M	155559915	0	0	0
RoundRobin_A	155559915	0	0	0
ValidKnown_A	155559915	125909200	0	0
gen_data_port_assertion.DataFlow_A	155559915	936686	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	125909200	0	0
T1	112770	112722	0	0
T2	136594	135542	0	0
T3	95550	94748	0	0
T4	136057	135440	0	0
T5	211252	211252	0	0
T6	20425	20425	0	0
T7	119178	0	0	0
T8	144200	144200	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	0	391038	0	0
T13	0	524347	0	0
T14	0	379328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	936686	0	0
T3	95550	518	0	0
T4	136057	0	0	0
T5	211252	0	0	0
T6	20425	0	0	0
T7	119178	0	0	0
T8	144200	0	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	393231	1083	0	0
T13	0	7635	0	0
T14	0	1287	0	0
T15	0	130	0	0
T16	0	10760	0	0
T18	0	6627	0	0
T25	0	5274	0	0
T29	2232	0	0	0
T70	0	4	0	0
T71	0	4727	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	936686	0	0
T3	95550	518	0	0
T4	136057	0	0	0
T5	211252	0	0	0
T6	20425	0	0	0
T7	119178	0	0	0
T8	144200	0	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	393231	1083	0	0
T13	0	7635	0	0
T14	0	1287	0	0
T15	0	130	0	0
T16	0	10760	0	0
T18	0	6627	0	0
T25	0	5274	0	0
T29	2232	0	0	0
T70	0	4	0	0
T71	0	4727	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	125909200	0	0
T1	112770	112722	0	0
T2	136594	135542	0	0
T3	95550	94748	0	0
T4	136057	135440	0	0
T5	211252	211252	0	0
T6	20425	20425	0	0
T7	119178	0	0	0
T8	144200	144200	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	0	391038	0	0
T13	0	524347	0	0
T14	0	379328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	125909200	0	0
T1	112770	112722	0	0
T2	136594	135542	0	0
T3	95550	94748	0	0
T4	136057	135440	0	0
T5	211252	211252	0	0
T6	20425	20425	0	0
T7	119178	0	0	0
T8	144200	144200	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	0	391038	0	0
T13	0	524347	0	0
T14	0	379328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	936686	0	0
T3	95550	518	0	0
T4	136057	0	0	0
T5	211252	0	0	0
T6	20425	0	0	0
T7	119178	0	0	0
T8	144200	0	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	393231	1083	0	0
T13	0	7635	0	0
T14	0	1287	0	0
T15	0	130	0	0
T16	0	10760	0	0
T18	0	6627	0	0
T25	0	5274	0	0
T29	2232	0	0	0
T70	0	4	0	0
T71	0	4727	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	936686	0	0
T3	95550	518	0	0
T4	136057	0	0	0
T5	211252	0	0	0
T6	20425	0	0	0
T7	119178	0	0	0
T8	144200	0	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	393231	1083	0	0
T13	0	7635	0	0
T14	0	1287	0	0
T15	0	130	0	0
T16	0	10760	0	0
T18	0	6627	0	0
T25	0	5274	0	0
T29	2232	0	0	0
T70	0	4	0	0
T71	0	4727	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	936686	0	0
T3	95550	518	0	0
T4	136057	0	0	0
T5	211252	0	0	0
T6	20425	0	0	0
T7	119178	0	0	0
T8	144200	0	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	393231	1083	0	0
T13	0	7635	0	0
T14	0	1287	0	0
T15	0	130	0	0
T16	0	10760	0	0
T18	0	6627	0	0
T25	0	5274	0	0
T29	2232	0	0	0
T70	0	4	0	0
T71	0	4727	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	936686	0	0
T3	95550	518	0	0
T4	136057	0	0	0
T5	211252	0	0	0
T6	20425	0	0	0
T7	119178	0	0	0
T8	144200	0	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	393231	1083	0	0
T13	0	7635	0	0
T14	0	1287	0	0
T15	0	130	0	0
T16	0	10760	0	0
T18	0	6627	0	0
T25	0	5274	0	0
T29	2232	0	0	0
T70	0	4	0	0
T71	0	4727	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	125909200	0	0
T1	112770	112722	0	0
T2	136594	135542	0	0
T3	95550	94748	0	0
T4	136057	135440	0	0
T5	211252	211252	0	0
T6	20425	20425	0	0
T7	119178	0	0	0
T8	144200	144200	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	0	391038	0	0
T13	0	524347	0	0
T14	0	379328	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155559915	936686	0	0
T3	95550	518	0	0
T4	136057	0	0	0
T5	211252	0	0	0
T6	20425	0	0	0
T7	119178	0	0	0
T8	144200	0	0	0
T10	39412	0	0	0
T11	97626	0	0	0
T12	393231	1083	0	0
T13	0	7635	0	0
T14	0	1287	0	0
T15	0	130	0	0
T16	0	10760	0	0
T18	0	6627	0	0
T25	0	5274	0	0
T29	2232	0	0	0
T70	0	4	0	0
T71	0	4727	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	458618872	458529849	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	458618872	2373526	0	0
GntImpliesValid_A	458618872	2373526	0	0
GrantKnown_A	458618872	458529849	0	0
IdxKnown_A	458618872	458529849	0	0
IndexIsCorrect_A	458618872	2373526	0	0
LockArbDecision_A	458618872	0	0	0
NoReadyValidNoGrant_A	458618872	0	0	0
ReadyAndValidImplyGrant_A	458618872	2373526	0	0
ReqAndReadyImplyGrant_A	458618872	2373526	0	0
ReqImpliesValid_A	458618872	2373526	0	0
ReqStaysHighUntilGranted0_M	458618872	0	0	0
RoundRobin_A	458618872	7	0	976
ValidKnown_A	458618872	458529849	0	0
gen_data_port_assertion.DataFlow_A	458618872	2373526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	458529849	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	2373526	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	386430	966	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	200	0	0
T10	23035	285	0	0
T12	0	7705	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	2373526	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	386430	966	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	200	0	0
T10	23035	285	0	0
T12	0	7705	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	458529849	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	458529849	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	2373526	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	386430	966	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	200	0	0
T10	23035	285	0	0
T12	0	7705	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	2373526	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	386430	966	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	200	0	0
T10	23035	285	0	0
T12	0	7705	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	2373526	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	386430	966	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	200	0	0
T10	23035	285	0	0
T12	0	7705	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	2373526	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	386430	966	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	200	0	0
T10	23035	285	0	0
T12	0	7705	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	7	0	976
T25	247368	1	0	1
T26	475879	0	0	1
T27	710890	0	0	1
T28	1122	0	0	1
T38	467702	0	0	1
T39	20425	0	0	1
T40	15179	0	0	1
T43	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	66161	0	0	1
T68	28756	0	0	1
T69	1908	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	458529849	0	0
T1	31338	31280	0	0
T2	161267	161179	0	0
T3	386430	386340	0	0
T4	685461	685382	0	0
T5	107023	107014	0	0
T6	44268	44204	0	0
T7	130998	130902	0	0
T8	148096	148015	0	0
T9	3199	3109	0	0
T10	23035	22952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458618872	2373526	0	0
T1	31338	832	0	0
T2	161267	1664	0	0
T3	386430	966	0	0
T4	685461	832	0	0
T5	107023	832	0	0
T6	44268	832	0	0
T7	130998	0	0	0
T8	148096	832	0	0
T9	3199	200	0	0
T10	23035	285	0	0
T12	0	7705	0	0