Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2964 |
0 |
0 |
T95 |
5665 |
6 |
0 |
0 |
T96 |
5280 |
64 |
0 |
0 |
T97 |
4073 |
6 |
0 |
0 |
T98 |
100336 |
2 |
0 |
0 |
T99 |
14357 |
153 |
0 |
0 |
T100 |
2787 |
4 |
0 |
0 |
T101 |
5658 |
218 |
0 |
0 |
T106 |
3438 |
125 |
0 |
0 |
T113 |
5161 |
18 |
0 |
0 |
T116 |
10808 |
7 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2973 |
0 |
0 |
T95 |
5665 |
5 |
0 |
0 |
T98 |
100336 |
130 |
0 |
0 |
T116 |
10808 |
10 |
0 |
0 |
T118 |
11370 |
18 |
0 |
0 |
T121 |
3813 |
4 |
0 |
0 |
T124 |
111994 |
733 |
0 |
0 |
T125 |
41470 |
235 |
0 |
0 |
T128 |
11581 |
14 |
0 |
0 |
T145 |
12886 |
48 |
0 |
0 |
T151 |
5243 |
3 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2910 |
0 |
0 |
T95 |
5665 |
3 |
0 |
0 |
T98 |
100336 |
79 |
0 |
0 |
T116 |
10808 |
14 |
0 |
0 |
T118 |
11370 |
5 |
0 |
0 |
T121 |
3813 |
5 |
0 |
0 |
T124 |
111994 |
808 |
0 |
0 |
T125 |
41470 |
251 |
0 |
0 |
T128 |
11581 |
22 |
0 |
0 |
T145 |
12886 |
30 |
0 |
0 |
T151 |
5243 |
8 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3509 |
0 |
0 |
T98 |
100336 |
228 |
0 |
0 |
T116 |
10808 |
34 |
0 |
0 |
T118 |
11370 |
33 |
0 |
0 |
T121 |
3813 |
3 |
0 |
0 |
T124 |
111994 |
668 |
0 |
0 |
T125 |
41470 |
239 |
0 |
0 |
T128 |
11581 |
21 |
0 |
0 |
T144 |
3741 |
3 |
0 |
0 |
T145 |
12886 |
20 |
0 |
0 |
T151 |
5243 |
9 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
13264 |
0 |
0 |
T95 |
5665 |
10 |
0 |
0 |
T98 |
100336 |
1455 |
0 |
0 |
T116 |
10808 |
18 |
0 |
0 |
T118 |
11370 |
328 |
0 |
0 |
T124 |
111994 |
708 |
0 |
0 |
T125 |
41470 |
266 |
0 |
0 |
T128 |
11581 |
13 |
0 |
0 |
T144 |
3741 |
4 |
0 |
0 |
T145 |
12886 |
19 |
0 |
0 |
T151 |
5243 |
2 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
13324 |
0 |
0 |
T95 |
5665 |
9 |
0 |
0 |
T98 |
100336 |
2139 |
0 |
0 |
T116 |
10808 |
14 |
0 |
0 |
T118 |
11370 |
281 |
0 |
0 |
T121 |
3813 |
80 |
0 |
0 |
T124 |
111994 |
658 |
0 |
0 |
T125 |
41470 |
233 |
0 |
0 |
T128 |
11581 |
325 |
0 |
0 |
T144 |
3741 |
2 |
0 |
0 |
T145 |
12886 |
19 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
13654 |
0 |
0 |
T98 |
100336 |
2091 |
0 |
0 |
T116 |
10808 |
246 |
0 |
0 |
T118 |
11370 |
227 |
0 |
0 |
T124 |
111994 |
694 |
0 |
0 |
T125 |
41470 |
239 |
0 |
0 |
T128 |
11581 |
370 |
0 |
0 |
T144 |
3741 |
2 |
0 |
0 |
T145 |
12886 |
23 |
0 |
0 |
T151 |
5243 |
142 |
0 |
0 |
T152 |
41696 |
286 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
13504 |
0 |
0 |
T95 |
5665 |
83 |
0 |
0 |
T98 |
100336 |
2674 |
0 |
0 |
T116 |
10808 |
136 |
0 |
0 |
T118 |
11370 |
339 |
0 |
0 |
T124 |
111994 |
728 |
0 |
0 |
T125 |
41470 |
257 |
0 |
0 |
T128 |
11581 |
131 |
0 |
0 |
T144 |
3741 |
124 |
0 |
0 |
T145 |
12886 |
14 |
0 |
0 |
T151 |
5243 |
104 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
12979 |
0 |
0 |
T95 |
5665 |
66 |
0 |
0 |
T98 |
100336 |
2519 |
0 |
0 |
T116 |
10808 |
269 |
0 |
0 |
T118 |
11370 |
9 |
0 |
0 |
T121 |
3813 |
66 |
0 |
0 |
T124 |
111994 |
697 |
0 |
0 |
T125 |
41470 |
257 |
0 |
0 |
T128 |
11581 |
14 |
0 |
0 |
T144 |
3741 |
115 |
0 |
0 |
T145 |
12886 |
42 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
11911 |
0 |
0 |
T95 |
5665 |
88 |
0 |
0 |
T98 |
100336 |
1741 |
0 |
0 |
T116 |
10808 |
201 |
0 |
0 |
T118 |
11370 |
109 |
0 |
0 |
T124 |
111994 |
702 |
0 |
0 |
T125 |
41470 |
224 |
0 |
0 |
T128 |
11581 |
234 |
0 |
0 |
T144 |
3741 |
9 |
0 |
0 |
T145 |
12886 |
27 |
0 |
0 |
T151 |
5243 |
107 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
12038 |
0 |
0 |
T95 |
5665 |
57 |
0 |
0 |
T98 |
100336 |
1728 |
0 |
0 |
T116 |
10808 |
237 |
0 |
0 |
T118 |
11370 |
195 |
0 |
0 |
T124 |
111994 |
678 |
0 |
0 |
T125 |
41470 |
293 |
0 |
0 |
T128 |
11581 |
242 |
0 |
0 |
T144 |
3741 |
151 |
0 |
0 |
T145 |
12886 |
17 |
0 |
0 |
T151 |
5243 |
86 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
13684 |
0 |
0 |
T98 |
100336 |
1837 |
0 |
0 |
T116 |
10808 |
12 |
0 |
0 |
T118 |
11370 |
323 |
0 |
0 |
T121 |
3813 |
3 |
0 |
0 |
T124 |
111994 |
750 |
0 |
0 |
T125 |
41470 |
257 |
0 |
0 |
T128 |
11581 |
18 |
0 |
0 |
T144 |
3741 |
143 |
0 |
0 |
T145 |
12886 |
14 |
0 |
0 |
T151 |
5243 |
118 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6916 |
0 |
0 |
T95 |
5665 |
6 |
0 |
0 |
T98 |
100336 |
820 |
0 |
0 |
T116 |
10808 |
58 |
0 |
0 |
T118 |
11370 |
176 |
0 |
0 |
T121 |
3813 |
36 |
0 |
0 |
T124 |
111994 |
747 |
0 |
0 |
T125 |
41470 |
265 |
0 |
0 |
T128 |
11581 |
148 |
0 |
0 |
T144 |
3741 |
3 |
0 |
0 |
T145 |
12886 |
9 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6176 |
0 |
0 |
T95 |
5665 |
21 |
0 |
0 |
T98 |
100336 |
701 |
0 |
0 |
T116 |
10808 |
51 |
0 |
0 |
T118 |
11370 |
14 |
0 |
0 |
T121 |
3813 |
15 |
0 |
0 |
T124 |
111994 |
743 |
0 |
0 |
T125 |
41470 |
234 |
0 |
0 |
T128 |
11581 |
92 |
0 |
0 |
T144 |
3741 |
57 |
0 |
0 |
T145 |
12886 |
29 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6837 |
0 |
0 |
T95 |
5665 |
3 |
0 |
0 |
T98 |
100336 |
842 |
0 |
0 |
T116 |
10808 |
68 |
0 |
0 |
T118 |
11370 |
59 |
0 |
0 |
T121 |
3813 |
7 |
0 |
0 |
T124 |
111994 |
778 |
0 |
0 |
T125 |
41470 |
249 |
0 |
0 |
T128 |
11581 |
120 |
0 |
0 |
T144 |
3741 |
4 |
0 |
0 |
T145 |
12886 |
22 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6490 |
0 |
0 |
T95 |
5665 |
21 |
0 |
0 |
T98 |
100336 |
841 |
0 |
0 |
T116 |
10808 |
14 |
0 |
0 |
T118 |
11370 |
156 |
0 |
0 |
T121 |
3813 |
18 |
0 |
0 |
T124 |
111994 |
736 |
0 |
0 |
T125 |
41470 |
278 |
0 |
0 |
T128 |
11581 |
38 |
0 |
0 |
T144 |
3741 |
5 |
0 |
0 |
T145 |
12886 |
34 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6348 |
0 |
0 |
T95 |
5665 |
29 |
0 |
0 |
T98 |
100336 |
779 |
0 |
0 |
T116 |
10808 |
46 |
0 |
0 |
T118 |
11370 |
134 |
0 |
0 |
T121 |
3813 |
3 |
0 |
0 |
T124 |
111994 |
692 |
0 |
0 |
T125 |
41470 |
276 |
0 |
0 |
T128 |
11581 |
54 |
0 |
0 |
T144 |
3741 |
45 |
0 |
0 |
T145 |
12886 |
24 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6616 |
0 |
0 |
T95 |
5665 |
31 |
0 |
0 |
T98 |
100336 |
849 |
0 |
0 |
T116 |
10808 |
45 |
0 |
0 |
T118 |
11370 |
67 |
0 |
0 |
T121 |
3813 |
8 |
0 |
0 |
T124 |
111994 |
753 |
0 |
0 |
T125 |
41470 |
247 |
0 |
0 |
T128 |
11581 |
78 |
0 |
0 |
T144 |
3741 |
50 |
0 |
0 |
T145 |
12886 |
26 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6324 |
0 |
0 |
T95 |
5665 |
10 |
0 |
0 |
T98 |
100336 |
808 |
0 |
0 |
T116 |
10808 |
10 |
0 |
0 |
T118 |
11370 |
22 |
0 |
0 |
T124 |
111994 |
725 |
0 |
0 |
T125 |
41470 |
237 |
0 |
0 |
T128 |
11581 |
80 |
0 |
0 |
T144 |
3741 |
1 |
0 |
0 |
T145 |
12886 |
30 |
0 |
0 |
T151 |
5243 |
54 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6713 |
0 |
0 |
T95 |
5665 |
27 |
0 |
0 |
T98 |
100336 |
684 |
0 |
0 |
T116 |
10808 |
104 |
0 |
0 |
T118 |
11370 |
41 |
0 |
0 |
T121 |
3813 |
33 |
0 |
0 |
T124 |
111994 |
697 |
0 |
0 |
T125 |
41470 |
272 |
0 |
0 |
T128 |
11581 |
117 |
0 |
0 |
T144 |
3741 |
45 |
0 |
0 |
T145 |
12886 |
48 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6790 |
0 |
0 |
T95 |
5665 |
15 |
0 |
0 |
T98 |
100336 |
936 |
0 |
0 |
T116 |
10808 |
84 |
0 |
0 |
T118 |
11370 |
14 |
0 |
0 |
T121 |
3813 |
33 |
0 |
0 |
T124 |
111994 |
653 |
0 |
0 |
T125 |
41470 |
289 |
0 |
0 |
T128 |
11581 |
112 |
0 |
0 |
T144 |
3741 |
3 |
0 |
0 |
T145 |
12886 |
40 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6630 |
0 |
0 |
T95 |
5665 |
1 |
0 |
0 |
T98 |
100336 |
865 |
0 |
0 |
T116 |
10808 |
64 |
0 |
0 |
T118 |
11370 |
40 |
0 |
0 |
T121 |
3813 |
40 |
0 |
0 |
T124 |
111994 |
719 |
0 |
0 |
T125 |
41470 |
273 |
0 |
0 |
T128 |
11581 |
16 |
0 |
0 |
T144 |
3741 |
8 |
0 |
0 |
T145 |
12886 |
3 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6436 |
0 |
0 |
T98 |
100336 |
880 |
0 |
0 |
T116 |
10808 |
89 |
0 |
0 |
T118 |
11370 |
88 |
0 |
0 |
T124 |
111994 |
716 |
0 |
0 |
T125 |
41470 |
287 |
0 |
0 |
T128 |
11581 |
148 |
0 |
0 |
T144 |
3741 |
43 |
0 |
0 |
T145 |
12886 |
22 |
0 |
0 |
T151 |
5243 |
61 |
0 |
0 |
T152 |
41696 |
233 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6528 |
0 |
0 |
T95 |
5665 |
2 |
0 |
0 |
T98 |
100336 |
636 |
0 |
0 |
T116 |
10808 |
47 |
0 |
0 |
T118 |
11370 |
78 |
0 |
0 |
T121 |
3813 |
4 |
0 |
0 |
T124 |
111994 |
673 |
0 |
0 |
T125 |
41470 |
265 |
0 |
0 |
T128 |
11581 |
13 |
0 |
0 |
T144 |
3741 |
1 |
0 |
0 |
T145 |
12886 |
20 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6976 |
0 |
0 |
T95 |
5665 |
22 |
0 |
0 |
T98 |
100336 |
798 |
0 |
0 |
T116 |
10808 |
22 |
0 |
0 |
T118 |
11370 |
5 |
0 |
0 |
T124 |
111994 |
702 |
0 |
0 |
T125 |
41470 |
228 |
0 |
0 |
T128 |
11581 |
153 |
0 |
0 |
T145 |
12886 |
9 |
0 |
0 |
T151 |
5243 |
2 |
0 |
0 |
T152 |
41696 |
255 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6841 |
0 |
0 |
T95 |
5665 |
45 |
0 |
0 |
T98 |
100336 |
975 |
0 |
0 |
T116 |
10808 |
12 |
0 |
0 |
T118 |
11370 |
95 |
0 |
0 |
T121 |
3813 |
21 |
0 |
0 |
T124 |
111994 |
623 |
0 |
0 |
T125 |
41470 |
240 |
0 |
0 |
T128 |
11581 |
108 |
0 |
0 |
T144 |
3741 |
48 |
0 |
0 |
T145 |
12886 |
47 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6499 |
0 |
0 |
T98 |
100336 |
766 |
0 |
0 |
T116 |
10808 |
12 |
0 |
0 |
T118 |
11370 |
38 |
0 |
0 |
T121 |
3813 |
40 |
0 |
0 |
T124 |
111994 |
644 |
0 |
0 |
T125 |
41470 |
283 |
0 |
0 |
T128 |
11581 |
147 |
0 |
0 |
T145 |
12886 |
24 |
0 |
0 |
T151 |
5243 |
30 |
0 |
0 |
T152 |
41696 |
268 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
7109 |
0 |
0 |
T95 |
5665 |
21 |
0 |
0 |
T98 |
100336 |
602 |
0 |
0 |
T116 |
10808 |
61 |
0 |
0 |
T118 |
11370 |
154 |
0 |
0 |
T121 |
3813 |
21 |
0 |
0 |
T124 |
111994 |
728 |
0 |
0 |
T125 |
41470 |
259 |
0 |
0 |
T128 |
11581 |
134 |
0 |
0 |
T144 |
3741 |
53 |
0 |
0 |
T145 |
12886 |
23 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6245 |
0 |
0 |
T95 |
5665 |
37 |
0 |
0 |
T98 |
100336 |
561 |
0 |
0 |
T99 |
14357 |
1 |
0 |
0 |
T116 |
10808 |
68 |
0 |
0 |
T118 |
11370 |
44 |
0 |
0 |
T124 |
111994 |
685 |
0 |
0 |
T125 |
41470 |
248 |
0 |
0 |
T128 |
11581 |
14 |
0 |
0 |
T144 |
3741 |
4 |
0 |
0 |
T145 |
12886 |
34 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
7044 |
0 |
0 |
T95 |
5665 |
7 |
0 |
0 |
T98 |
100336 |
808 |
0 |
0 |
T116 |
10808 |
72 |
0 |
0 |
T118 |
11370 |
90 |
0 |
0 |
T121 |
3813 |
4 |
0 |
0 |
T124 |
111994 |
732 |
0 |
0 |
T125 |
41470 |
256 |
0 |
0 |
T128 |
11581 |
95 |
0 |
0 |
T144 |
3741 |
60 |
0 |
0 |
T145 |
12886 |
6 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6450 |
0 |
0 |
T95 |
5665 |
24 |
0 |
0 |
T98 |
100336 |
733 |
0 |
0 |
T116 |
10808 |
58 |
0 |
0 |
T118 |
11370 |
122 |
0 |
0 |
T121 |
3813 |
29 |
0 |
0 |
T124 |
111994 |
725 |
0 |
0 |
T125 |
41470 |
244 |
0 |
0 |
T128 |
11581 |
93 |
0 |
0 |
T144 |
3741 |
4 |
0 |
0 |
T145 |
12886 |
20 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6448 |
0 |
0 |
T95 |
5665 |
51 |
0 |
0 |
T98 |
100336 |
761 |
0 |
0 |
T116 |
10808 |
46 |
0 |
0 |
T118 |
11370 |
43 |
0 |
0 |
T121 |
3813 |
3 |
0 |
0 |
T124 |
111994 |
683 |
0 |
0 |
T125 |
41470 |
280 |
0 |
0 |
T128 |
11581 |
64 |
0 |
0 |
T144 |
3741 |
52 |
0 |
0 |
T145 |
12886 |
11 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6693 |
0 |
0 |
T95 |
5665 |
7 |
0 |
0 |
T98 |
100336 |
914 |
0 |
0 |
T116 |
10808 |
38 |
0 |
0 |
T118 |
11370 |
43 |
0 |
0 |
T121 |
3813 |
18 |
0 |
0 |
T124 |
111994 |
774 |
0 |
0 |
T125 |
41470 |
252 |
0 |
0 |
T128 |
11581 |
109 |
0 |
0 |
T144 |
3741 |
5 |
0 |
0 |
T145 |
12886 |
5 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6448 |
0 |
0 |
T95 |
5665 |
14 |
0 |
0 |
T98 |
100336 |
776 |
0 |
0 |
T116 |
10808 |
132 |
0 |
0 |
T118 |
11370 |
42 |
0 |
0 |
T121 |
3813 |
16 |
0 |
0 |
T124 |
111994 |
697 |
0 |
0 |
T125 |
41470 |
304 |
0 |
0 |
T128 |
11581 |
74 |
0 |
0 |
T144 |
3741 |
4 |
0 |
0 |
T145 |
12886 |
10 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
7005 |
0 |
0 |
T95 |
5665 |
33 |
0 |
0 |
T98 |
100336 |
789 |
0 |
0 |
T116 |
10808 |
63 |
0 |
0 |
T118 |
11370 |
32 |
0 |
0 |
T121 |
3813 |
1 |
0 |
0 |
T124 |
111994 |
770 |
0 |
0 |
T125 |
41470 |
212 |
0 |
0 |
T128 |
11581 |
141 |
0 |
0 |
T144 |
3741 |
58 |
0 |
0 |
T145 |
12886 |
2 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
6295 |
0 |
0 |
T95 |
5665 |
1 |
0 |
0 |
T98 |
100336 |
647 |
0 |
0 |
T116 |
10808 |
71 |
0 |
0 |
T118 |
11370 |
37 |
0 |
0 |
T124 |
111994 |
694 |
0 |
0 |
T125 |
41470 |
244 |
0 |
0 |
T128 |
11581 |
110 |
0 |
0 |
T145 |
12886 |
37 |
0 |
0 |
T151 |
5243 |
7 |
0 |
0 |
T152 |
41696 |
253 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3318 |
0 |
0 |
T95 |
5665 |
8 |
0 |
0 |
T98 |
100336 |
128 |
0 |
0 |
T116 |
10808 |
25 |
0 |
0 |
T118 |
11370 |
15 |
0 |
0 |
T121 |
3813 |
8 |
0 |
0 |
T124 |
111994 |
823 |
0 |
0 |
T125 |
41470 |
214 |
0 |
0 |
T128 |
11581 |
13 |
0 |
0 |
T145 |
12886 |
31 |
0 |
0 |
T151 |
5243 |
4 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3127 |
0 |
0 |
T95 |
5665 |
4 |
0 |
0 |
T98 |
100336 |
158 |
0 |
0 |
T116 |
10808 |
10 |
0 |
0 |
T118 |
11370 |
6 |
0 |
0 |
T124 |
111994 |
656 |
0 |
0 |
T125 |
41470 |
279 |
0 |
0 |
T128 |
11581 |
16 |
0 |
0 |
T145 |
12886 |
10 |
0 |
0 |
T151 |
5243 |
3 |
0 |
0 |
T152 |
41696 |
282 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3246 |
0 |
0 |
T95 |
5665 |
2 |
0 |
0 |
T98 |
100336 |
162 |
0 |
0 |
T116 |
10808 |
19 |
0 |
0 |
T118 |
11370 |
19 |
0 |
0 |
T121 |
3813 |
2 |
0 |
0 |
T124 |
111994 |
780 |
0 |
0 |
T125 |
41470 |
265 |
0 |
0 |
T128 |
11581 |
26 |
0 |
0 |
T144 |
3741 |
15 |
0 |
0 |
T145 |
12886 |
23 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2969 |
0 |
0 |
T95 |
5665 |
2 |
0 |
0 |
T98 |
100336 |
162 |
0 |
0 |
T116 |
10808 |
29 |
0 |
0 |
T118 |
11370 |
11 |
0 |
0 |
T124 |
111994 |
678 |
0 |
0 |
T125 |
41470 |
230 |
0 |
0 |
T128 |
11581 |
24 |
0 |
0 |
T144 |
3741 |
13 |
0 |
0 |
T145 |
12886 |
34 |
0 |
0 |
T151 |
5243 |
2 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3950 |
0 |
0 |
T95 |
5665 |
10 |
0 |
0 |
T98 |
100336 |
313 |
0 |
0 |
T116 |
10808 |
44 |
0 |
0 |
T118 |
11370 |
15 |
0 |
0 |
T124 |
111994 |
646 |
0 |
0 |
T125 |
41470 |
257 |
0 |
0 |
T128 |
11581 |
9 |
0 |
0 |
T144 |
3741 |
4 |
0 |
0 |
T145 |
12886 |
21 |
0 |
0 |
T151 |
5243 |
2 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
5718 |
0 |
0 |
T15 |
27602 |
5 |
0 |
0 |
T16 |
0 |
13 |
0 |
0 |
T21 |
0 |
43 |
0 |
0 |
T23 |
4391 |
0 |
0 |
0 |
T24 |
3996 |
0 |
0 |
0 |
T25 |
247368 |
0 |
0 |
0 |
T26 |
475879 |
0 |
0 |
0 |
T27 |
710890 |
0 |
0 |
0 |
T28 |
1122 |
0 |
0 |
0 |
T38 |
467702 |
0 |
0 |
0 |
T39 |
20425 |
0 |
0 |
0 |
T40 |
15179 |
0 |
0 |
0 |
T153 |
0 |
41 |
0 |
0 |
T154 |
0 |
13 |
0 |
0 |
T155 |
0 |
5 |
0 |
0 |
T156 |
0 |
27 |
0 |
0 |
T157 |
0 |
4 |
0 |
0 |
T158 |
0 |
41 |
0 |
0 |
T159 |
0 |
25 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3141 |
0 |
0 |
T95 |
5665 |
10 |
0 |
0 |
T98 |
100336 |
150 |
0 |
0 |
T116 |
10808 |
11 |
0 |
0 |
T118 |
11370 |
22 |
0 |
0 |
T121 |
3813 |
7 |
0 |
0 |
T124 |
111994 |
727 |
0 |
0 |
T125 |
41470 |
224 |
0 |
0 |
T128 |
11581 |
17 |
0 |
0 |
T144 |
3741 |
8 |
0 |
0 |
T145 |
12886 |
11 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3132 |
0 |
0 |
T98 |
100336 |
156 |
0 |
0 |
T116 |
10808 |
23 |
0 |
0 |
T118 |
11370 |
13 |
0 |
0 |
T121 |
3813 |
7 |
0 |
0 |
T124 |
111994 |
739 |
0 |
0 |
T125 |
41470 |
268 |
0 |
0 |
T128 |
11581 |
18 |
0 |
0 |
T144 |
3741 |
7 |
0 |
0 |
T145 |
12886 |
22 |
0 |
0 |
T151 |
5243 |
3 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2762 |
0 |
0 |
T95 |
5665 |
4 |
0 |
0 |
T98 |
100336 |
92 |
0 |
0 |
T116 |
10808 |
24 |
0 |
0 |
T118 |
11370 |
15 |
0 |
0 |
T124 |
111994 |
664 |
0 |
0 |
T125 |
41470 |
254 |
0 |
0 |
T128 |
11581 |
6 |
0 |
0 |
T144 |
3741 |
7 |
0 |
0 |
T145 |
12886 |
13 |
0 |
0 |
T151 |
5243 |
4 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2737 |
0 |
0 |
T95 |
5665 |
2 |
0 |
0 |
T98 |
100336 |
116 |
0 |
0 |
T99 |
14357 |
6 |
0 |
0 |
T116 |
10808 |
7 |
0 |
0 |
T118 |
11370 |
4 |
0 |
0 |
T121 |
3813 |
6 |
0 |
0 |
T124 |
111994 |
705 |
0 |
0 |
T125 |
41470 |
203 |
0 |
0 |
T144 |
3741 |
1 |
0 |
0 |
T145 |
12886 |
16 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2774 |
0 |
0 |
T98 |
100336 |
130 |
0 |
0 |
T116 |
10808 |
15 |
0 |
0 |
T118 |
11370 |
10 |
0 |
0 |
T124 |
111994 |
729 |
0 |
0 |
T125 |
41470 |
205 |
0 |
0 |
T128 |
11581 |
11 |
0 |
0 |
T144 |
3741 |
9 |
0 |
0 |
T145 |
12886 |
23 |
0 |
0 |
T151 |
5243 |
1 |
0 |
0 |
T152 |
41696 |
252 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2951 |
0 |
0 |
T98 |
100336 |
116 |
0 |
0 |
T116 |
10808 |
24 |
0 |
0 |
T118 |
11370 |
8 |
0 |
0 |
T124 |
111994 |
784 |
0 |
0 |
T125 |
41470 |
252 |
0 |
0 |
T128 |
11581 |
7 |
0 |
0 |
T144 |
3741 |
6 |
0 |
0 |
T145 |
12886 |
11 |
0 |
0 |
T151 |
5243 |
2 |
0 |
0 |
T152 |
41696 |
219 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3730 |
0 |
0 |
T95 |
5665 |
7 |
0 |
0 |
T98 |
100336 |
253 |
0 |
0 |
T116 |
10808 |
45 |
0 |
0 |
T118 |
11370 |
40 |
0 |
0 |
T121 |
3813 |
6 |
0 |
0 |
T124 |
111994 |
752 |
0 |
0 |
T125 |
41470 |
257 |
0 |
0 |
T128 |
11581 |
48 |
0 |
0 |
T144 |
3741 |
6 |
0 |
0 |
T145 |
12886 |
19 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2913 |
0 |
0 |
T95 |
5665 |
2 |
0 |
0 |
T98 |
100336 |
107 |
0 |
0 |
T116 |
10808 |
13 |
0 |
0 |
T118 |
11370 |
19 |
0 |
0 |
T121 |
3813 |
5 |
0 |
0 |
T124 |
111994 |
764 |
0 |
0 |
T125 |
41470 |
272 |
0 |
0 |
T128 |
11581 |
7 |
0 |
0 |
T144 |
3741 |
9 |
0 |
0 |
T145 |
12886 |
44 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3881 |
0 |
0 |
T98 |
100336 |
290 |
0 |
0 |
T116 |
10808 |
55 |
0 |
0 |
T118 |
11370 |
17 |
0 |
0 |
T124 |
111994 |
738 |
0 |
0 |
T125 |
41470 |
230 |
0 |
0 |
T128 |
11581 |
21 |
0 |
0 |
T144 |
3741 |
27 |
0 |
0 |
T145 |
12886 |
27 |
0 |
0 |
T152 |
41696 |
230 |
0 |
0 |
T160 |
9946 |
36 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
3149 |
0 |
0 |
T98 |
100336 |
178 |
0 |
0 |
T116 |
10808 |
28 |
0 |
0 |
T118 |
11370 |
17 |
0 |
0 |
T121 |
3813 |
8 |
0 |
0 |
T124 |
111994 |
696 |
0 |
0 |
T125 |
41470 |
253 |
0 |
0 |
T128 |
11581 |
20 |
0 |
0 |
T144 |
3741 |
3 |
0 |
0 |
T145 |
12886 |
11 |
0 |
0 |
T151 |
5243 |
1 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2755 |
0 |
0 |
T95 |
5665 |
11 |
0 |
0 |
T98 |
100336 |
153 |
0 |
0 |
T116 |
10808 |
7 |
0 |
0 |
T118 |
11370 |
12 |
0 |
0 |
T121 |
3813 |
3 |
0 |
0 |
T124 |
111994 |
685 |
0 |
0 |
T125 |
41470 |
252 |
0 |
0 |
T128 |
11581 |
6 |
0 |
0 |
T144 |
3741 |
4 |
0 |
0 |
T145 |
12886 |
28 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2715 |
0 |
0 |
T98 |
100336 |
94 |
0 |
0 |
T116 |
10808 |
14 |
0 |
0 |
T118 |
11370 |
15 |
0 |
0 |
T124 |
111994 |
645 |
0 |
0 |
T125 |
41470 |
279 |
0 |
0 |
T128 |
11581 |
6 |
0 |
0 |
T144 |
3741 |
8 |
0 |
0 |
T145 |
12886 |
23 |
0 |
0 |
T151 |
5243 |
5 |
0 |
0 |
T152 |
41696 |
251 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2904 |
0 |
0 |
T95 |
5665 |
7 |
0 |
0 |
T98 |
100336 |
137 |
0 |
0 |
T116 |
10808 |
22 |
0 |
0 |
T118 |
11370 |
16 |
0 |
0 |
T121 |
3813 |
9 |
0 |
0 |
T124 |
111994 |
734 |
0 |
0 |
T125 |
41470 |
265 |
0 |
0 |
T128 |
11581 |
18 |
0 |
0 |
T144 |
3741 |
1 |
0 |
0 |
T145 |
12886 |
17 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2906 |
0 |
0 |
T95 |
5665 |
5 |
0 |
0 |
T98 |
100336 |
126 |
0 |
0 |
T116 |
10808 |
18 |
0 |
0 |
T118 |
11370 |
7 |
0 |
0 |
T124 |
111994 |
715 |
0 |
0 |
T125 |
41470 |
269 |
0 |
0 |
T128 |
11581 |
9 |
0 |
0 |
T144 |
3741 |
3 |
0 |
0 |
T145 |
12886 |
11 |
0 |
0 |
T151 |
5243 |
3 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2812 |
0 |
0 |
T95 |
5665 |
9 |
0 |
0 |
T98 |
100336 |
114 |
0 |
0 |
T116 |
10808 |
26 |
0 |
0 |
T118 |
11370 |
11 |
0 |
0 |
T124 |
111994 |
670 |
0 |
0 |
T125 |
41470 |
262 |
0 |
0 |
T128 |
11581 |
14 |
0 |
0 |
T144 |
3741 |
9 |
0 |
0 |
T145 |
12886 |
7 |
0 |
0 |
T151 |
5243 |
3 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
461077714 |
2807 |
0 |
0 |
T98 |
100336 |
106 |
0 |
0 |
T116 |
10808 |
17 |
0 |
0 |
T118 |
11370 |
13 |
0 |
0 |
T124 |
111994 |
703 |
0 |
0 |
T125 |
41470 |
224 |
0 |
0 |
T128 |
11581 |
3 |
0 |
0 |
T144 |
3741 |
1 |
0 |
0 |
T145 |
12886 |
27 |
0 |
0 |
T151 |
5243 |
2 |
0 |
0 |
T152 |
41696 |
273 |
0 |
0 |