Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4248474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4722405

1

T1

196

T2

875

T3

895

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4987489	1			T1	1		T2	2		T3	38
values[0x0]	1990847	1			T1	116		T2	452		T3	425
values[0x1]	1992543	1			T1	120		T2	424		T3	455

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3002197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5968682

1

T1

205

T2

875

T3

898

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36294	1			T1	3		T2	4		T3	7
valid_sources[0x01]	33237	1			T3	8		T7	3		T12	113
valid_sources[0x02]	33721	1			T1	1		T2	1		T3	2
valid_sources[0x03]	34727	1			T2	3		T3	2		T4	650
valid_sources[0x04]	37585	1			T1	14		T2	7		T3	1
valid_sources[0x05]	41570	1			T2	3		T12	97		T13	93
valid_sources[0x06]	36982	1			T1	2		T2	3		T3	6
valid_sources[0x07]	31730	1			T1	5		T2	5		T3	2
valid_sources[0x08]	32364	1			T1	5		T2	5		T7	2
valid_sources[0x09]	41169	1			T2	6		T3	4		T4	4
valid_sources[0x0a]	32829	1			T2	4		T12	95		T13	87
valid_sources[0x0b]	36693	1			T1	1		T2	3		T3	3
valid_sources[0x0c]	34876	1			T2	4		T3	5		T4	206
valid_sources[0x0d]	33246	1			T2	5		T3	10		T4	16
valid_sources[0x0e]	36607	1			T2	1		T3	4		T4	305
valid_sources[0x0f]	31786	1			T2	5		T4	2		T7	2
valid_sources[0x10]	33169	1			T2	2		T3	7		T11	3
valid_sources[0x11]	31180	1			T2	5		T3	6		T7	1
valid_sources[0x12]	39219	1			T1	3		T2	2		T3	6
valid_sources[0x13]	31416	1			T1	2		T2	1		T3	12
valid_sources[0x14]	44484	1			T2	3		T3	7		T7	12
valid_sources[0x15]	33209	1			T1	4		T2	2		T3	4
valid_sources[0x16]	38037	1			T2	4		T4	1		T8	3
valid_sources[0x17]	34463	1			T1	2		T2	4		T4	2
valid_sources[0x18]	55283	1			T2	4		T12	98		T13	63
valid_sources[0x19]	35635	1			T2	3		T3	1		T7	1
valid_sources[0x1a]	33353	1			T2	7		T3	7		T4	1
valid_sources[0x1b]	31591	1			T2	3		T3	4		T4	1
valid_sources[0x1c]	32913	1			T1	2		T2	5		T3	7
valid_sources[0x1d]	34828	1			T2	5		T3	9		T12	112
valid_sources[0x1e]	34255	1			T1	4		T2	4		T3	9
valid_sources[0x1f]	33000	1			T1	3		T2	7		T3	1
valid_sources[0x20]	39820	1			T1	5		T2	5		T3	5
valid_sources[0x21]	32489	1			T2	1		T3	5		T4	334
valid_sources[0x22]	32965	1			T2	1		T11	11		T12	109
valid_sources[0x23]	34064	1			T2	2		T3	1		T8	20
valid_sources[0x24]	31272	1			T2	4		T3	12		T11	10
valid_sources[0x25]	36147	1			T1	5		T2	4		T3	1
valid_sources[0x26]	33609	1			T2	7		T3	2		T12	78
valid_sources[0x27]	30716	1			T2	1		T3	4		T7	4
valid_sources[0x28]	34671	1			T1	2		T2	3		T3	5
valid_sources[0x29]	32351	1			T2	5		T3	1		T7	3
valid_sources[0x2a]	34944	1			T1	3		T2	2		T3	5
valid_sources[0x2b]	31637	1			T1	1		T2	1		T3	14
valid_sources[0x2c]	30690	1			T2	6		T3	2		T7	3
valid_sources[0x2d]	33288	1			T2	3		T3	5		T4	38
valid_sources[0x2e]	32166	1			T1	1		T2	4		T3	9
valid_sources[0x2f]	34801	1			T1	1		T2	4		T3	1
valid_sources[0x30]	34251	1			T2	2		T3	5		T7	2
valid_sources[0x31]	34274	1			T2	2		T3	1		T7	1
valid_sources[0x32]	31116	1			T1	2		T2	4		T3	2
valid_sources[0x33]	35317	1			T1	1		T2	4		T12	102
valid_sources[0x34]	31106	1			T2	2		T4	3		T7	3
valid_sources[0x35]	33836	1			T2	2		T3	6		T7	2
valid_sources[0x36]	38583	1			T2	3		T12	104		T13	86
valid_sources[0x37]	35036	1			T2	2		T3	13		T11	4
valid_sources[0x38]	34198	1			T2	2		T3	5		T4	4
valid_sources[0x39]	32813	1			T2	6		T3	9		T12	95
valid_sources[0x3a]	35732	1			T2	2		T8	3		T11	1
valid_sources[0x3b]	33767	1			T2	3		T3	2		T8	14
valid_sources[0x3c]	30116	1			T2	5		T3	8		T7	5
valid_sources[0x3d]	37150	1			T2	1		T7	4		T11	54
valid_sources[0x3e]	35134	1			T1	5		T2	3		T3	2
valid_sources[0x3f]	32579	1			T1	4		T2	7		T3	1
valid_sources[0x40]	35207	1			T1	1		T2	2		T11	13
valid_sources[0x41]	52474	1			T2	5		T3	4		T4	513
valid_sources[0x42]	32839	1			T2	4		T7	2		T8	5
valid_sources[0x43]	32647	1			T2	5		T4	1		T8	10
valid_sources[0x44]	37792	1			T1	3		T2	3		T3	3
valid_sources[0x45]	37136	1			T2	1		T3	1		T7	1
valid_sources[0x46]	32524	1			T2	3		T12	95		T13	78
valid_sources[0x47]	33415	1			T2	3		T3	3		T4	4
valid_sources[0x48]	36120	1			T2	3		T3	15		T4	112
valid_sources[0x49]	31928	1			T2	3		T3	13		T12	102
valid_sources[0x4a]	35856	1			T1	1		T2	6		T3	4
valid_sources[0x4b]	30685	1			T1	5		T2	2		T11	18
valid_sources[0x4c]	36485	1			T2	1		T3	5		T4	6
valid_sources[0x4d]	32686	1			T2	3		T3	5		T7	1
valid_sources[0x4e]	38011	1			T2	2		T3	11		T7	1
valid_sources[0x4f]	34135	1			T2	3		T3	2		T12	81
valid_sources[0x50]	33776	1			T2	4		T11	21		T12	107
valid_sources[0x51]	34764	1			T2	1		T3	2		T8	35
valid_sources[0x52]	33499	1			T2	4		T3	3		T4	3
valid_sources[0x53]	34295	1			T2	4		T3	15		T4	1
valid_sources[0x54]	32486	1			T1	1		T2	2		T3	4
valid_sources[0x55]	36214	1			T1	1		T2	2		T3	4
valid_sources[0x56]	32416	1			T2	5		T3	6		T12	86
valid_sources[0x57]	30889	1			T1	5		T2	3		T3	7
valid_sources[0x58]	32143	1			T7	2		T12	95		T13	73
valid_sources[0x59]	32851	1			T2	4		T3	2		T8	16
valid_sources[0x5a]	32496	1			T1	1		T2	2		T3	38
valid_sources[0x5b]	30150	1			T2	6		T3	3		T5	10
valid_sources[0x5c]	32979	1			T2	2		T7	3		T12	100
valid_sources[0x5d]	32805	1			T1	2		T2	4		T3	3
valid_sources[0x5e]	53181	1			T2	3		T3	5		T4	573
valid_sources[0x5f]	38958	1			T2	1		T4	114		T12	76
valid_sources[0x60]	33197	1			T1	3		T2	4		T11	9
valid_sources[0x61]	32654	1			T1	1		T2	4		T3	2
valid_sources[0x62]	34334	1			T2	1		T3	1		T7	2
valid_sources[0x63]	37104	1			T1	1		T2	3		T3	7
valid_sources[0x64]	34374	1			T2	6		T3	3		T12	86
valid_sources[0x65]	33851	1			T1	4		T2	5		T3	1
valid_sources[0x66]	31755	1			T2	3		T8	5		T12	68
valid_sources[0x67]	34244	1			T2	2		T3	3		T4	3
valid_sources[0x68]	34581	1			T2	2		T3	1		T7	1
valid_sources[0x69]	38171	1			T2	4		T3	6		T7	6
valid_sources[0x6a]	34056	1			T2	9		T3	1		T11	4
valid_sources[0x6b]	34337	1			T2	3		T3	2		T4	27
valid_sources[0x6c]	31523	1			T1	9		T2	2		T4	2
valid_sources[0x6d]	30977	1			T2	5		T3	2		T5	13
valid_sources[0x6e]	33153	1			T2	5		T3	9		T4	4
valid_sources[0x6f]	38750	1			T2	2		T3	2		T7	1
valid_sources[0x70]	38155	1			T2	2		T3	6		T5	2
valid_sources[0x71]	32035	1			T2	4		T8	6		T12	83
valid_sources[0x72]	31181	1			T2	2		T3	1		T4	1
valid_sources[0x73]	32516	1			T1	4		T2	5		T3	4
valid_sources[0x74]	32444	1			T1	1		T2	3		T7	3
valid_sources[0x75]	35629	1			T3	1		T9	1		T12	93
valid_sources[0x76]	36328	1			T1	1		T3	8		T6	2
valid_sources[0x77]	38130	1			T1	1		T2	10		T3	20
valid_sources[0x78]	34861	1			T1	4		T2	2		T4	3
valid_sources[0x79]	35523	1			T1	2		T2	8		T3	2
valid_sources[0x7a]	37220	1			T2	5		T8	10		T11	1
valid_sources[0x7b]	32091	1			T2	7		T3	1		T4	41
valid_sources[0x7c]	41912	1			T1	3		T2	5		T4	510
valid_sources[0x7d]	36294	1			T2	3		T3	2		T7	1
valid_sources[0x7e]	32022	1			T1	5		T2	4		T3	2
valid_sources[0x7f]	34780	1			T1	2		T2	3		T3	8
valid_sources[0x80]	33026	1			T2	2		T7	2		T12	77

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1134460

1

T1

1

T2

1

T3

19

values[0x0]

all_enables

biggest_size

1807037

1

T1

97

T2

450

T3

425

values[0x1]

all_enables

biggest_size

1780908

1

T1

98

T2

424

T3

451