Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4267567

1

T1

41

T2

3

T3

23

full_word

4721380

1

T1

196

T2

875

T3

895

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8988527	1			T1	237		T2	878		T3	918
auto[TlIntgErrCmd]	141	1			T93	6		T94	6		T98	2
auto[TlIntgErrData]	139	1			T93	2		T94	7		T98	4
auto[TlIntgErrBoth]	140	1			T93	2		T94	7		T98	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4988760

1

T1

1

T2

2

T3

38

auto[1]

4000187

1

T1

236

T2

876

T3

880

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3854016	1			T2	1		T3	19		T4	4701
auto[TlIntgErrNone]	partial	auto[1]	413164	1			T1	41		T2	2		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1134548	1			T1	1		T2	1		T3	19
auto[TlIntgErrNone]	full_word	auto[1]	3586799	1			T1	195		T2	874		T3	876
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T93	1		T94	3		T98	2
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T93	5		T94	2		T144	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T94	1		T164	2		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T109	1		T165	1		T166	1
auto[TlIntgErrData]	partial	auto[0]	71	1			T94	2		T98	2		T144	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T93	2		T94	4		T98	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T167	1		T165	1		T166	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T94	1		T167	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T93	1		T94	3		T98	3
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T93	1		T94	3		T98	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T164	1		T169	1		T168	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T94	1		T165	1		T164	1