Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	504049421	3077476	0	0
DepthKnown_A	504049421	503912566	0	0
RvalidKnown_A	504049421	503912566	0	0
WreadyKnown_A	504049421	503912566	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	3077476	0	0
T2	15336	1663	0	0
T3	3902	832	0	0
T4	425150	0	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	1664	0	0
T12	0	19987	0	0
T13	0	7487	0	0
T14	0	6653	0	0
T15	0	832	0	0
T16	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	504049421	3671748	0	0
DepthKnown_A	504049421	503912566	0	0
RvalidKnown_A	504049421	503912566	0	0
WreadyKnown_A	504049421	503912566	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	3671748	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	0	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	833	0	0
T12	0	23969	0	0
T13	0	13773	0	0
T14	0	4160	0	0
T15	0	832	0	0
T16	0	3783	0	0
T23	1185	0	0	0
T24	0	2555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	504049421	208923	0	0
DepthKnown_A	504049421	503912566	0	0
RvalidKnown_A	504049421	503912566	0	0
WreadyKnown_A	504049421	503912566	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	208923	0	0
T4	425150	675	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	0	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	865915	0	0	0
T12	571058	1433	0	0
T13	0	264	0	0
T14	0	64	0	0
T16	0	128	0	0
T17	0	605	0	0
T23	1185	0	0	0
T27	0	808	0	0
T28	0	1544	0	0
T39	0	110	0	0
T40	0	453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	504049421	532912	0	0
DepthKnown_A	504049421	503912566	0	0
RvalidKnown_A	504049421	503912566	0	0
WreadyKnown_A	504049421	503912566	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	532912	0	0
T4	425150	3181	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	0	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	865915	0	0	0
T12	571058	6542	0	0
T13	0	1153	0	0
T14	0	64	0	0
T16	0	541	0	0
T17	0	605	0	0
T23	1185	0	0	0
T27	0	808	0	0
T28	0	1538	0	0
T39	0	110	0	0
T40	0	453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	504049421	7223847	0	0
DepthKnown_A	504049421	503912566	0	0
RvalidKnown_A	504049421	503912566	0	0
WreadyKnown_A	504049421	503912566	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	7223847	0	0
T1	38666	237	0	0
T2	15336	46	0	0
T3	3902	86	0	0
T4	425150	8349	0	0
T5	1263	41	0	0
T6	793	2	0	0
T7	49324	285	0	0
T8	18551	928	0	0
T9	4593	17	0	0
T10	1729	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	504049421	15825508	0	0
DepthKnown_A	504049421	503912566	0	0
RvalidKnown_A	504049421	503912566	0	0
WreadyKnown_A	504049421	503912566	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	15825508	0	0
T1	38666	1096	0	0
T2	15336	153	0	0
T3	3902	86	0	0
T4	425150	35431	0	0
T5	1263	41	0	0
T6	793	13	0	0
T7	49324	1242	0	0
T8	18551	927	0	0
T9	4593	79	0	0
T10	1729	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504049421	503912566	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0