Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Unreachable
1	1	Covered	T4,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T12,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	822574582	660404243	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	822574582	4028071	0	0
GntImpliesValid_A	822574582	4028071	0	0
GrantKnown_A	822574582	660404243	0	0
IdxKnown_A	822574582	660404243	0	0
IndexIsCorrect_A	822574582	4028071	0	0
LockArbDecision_A	822574582	0	0	0
NoReadyValidNoGrant_A	822574582	0	0	0
ReadyAndValidImplyGrant_A	822574582	4028071	0	0
ReqAndReadyImplyGrant_A	822574582	4028071	0	0
ReqImpliesValid_A	822574582	4028071	0	0
ReqStaysHighUntilGranted0_M	822574582	0	0	0
RoundRobin_A	822574582	4	0	976
ValidKnown_A	822574582	660404243	0	0
gen_data_port_assertion.DataFlow_A	822574582	4028071	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	660404243	0	0
T1	88485	86095	0	0
T2	86348	50745	0	0
T3	11326	7559	0	0
T4	640760	529392	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	294678	162268	0	0
T8	23655	21034	0	0
T9	5313	4883	0	0
T10	1729	1652	0	0
T11	287420	143710	0	0
T12	1331152	656301	0	0
T13	537366	265163	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	169971	0	0
T25	68287	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4028071	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	532955	6389	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	172001	0	0	0
T8	21103	832	0	0
T9	4953	0	0	0
T10	1729	0	0	0
T11	143710	832	0	0
T12	1331152	22093	0	0
T13	537366	6945	0	0
T14	481558	4492	0	0
T15	6624	832	0	0
T16	27977	514	0	0
T17	176750	3241	0	0
T19	0	5823	0	0
T20	0	16080	0	0
T21	0	5651	0	0
T23	1185	0	0	0
T24	0	832	0	0
T25	136574	0	0	0
T26	52630	0	0	0
T27	0	5049	0	0
T28	0	18744	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0
T46	0	2997	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4028071	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	532955	6389	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	172001	0	0	0
T8	21103	832	0	0
T9	4953	0	0	0
T10	1729	0	0	0
T11	143710	832	0	0
T12	1331152	22093	0	0
T13	537366	6945	0	0
T14	481558	4492	0	0
T15	6624	832	0	0
T16	27977	514	0	0
T17	176750	3241	0	0
T19	0	5823	0	0
T20	0	16080	0	0
T21	0	5651	0	0
T23	1185	0	0	0
T24	0	832	0	0
T25	136574	0	0	0
T26	52630	0	0	0
T27	0	5049	0	0
T28	0	18744	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0
T46	0	2997	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	660404243	0	0
T1	88485	86095	0	0
T2	86348	50745	0	0
T3	11326	7559	0	0
T4	640760	529392	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	294678	162268	0	0
T8	23655	21034	0	0
T9	5313	4883	0	0
T10	1729	1652	0	0
T11	287420	143710	0	0
T12	1331152	656301	0	0
T13	537366	265163	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	169971	0	0
T25	68287	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	660404243	0	0
T1	88485	86095	0	0
T2	86348	50745	0	0
T3	11326	7559	0	0
T4	640760	529392	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	294678	162268	0	0
T8	23655	21034	0	0
T9	5313	4883	0	0
T10	1729	1652	0	0
T11	287420	143710	0	0
T12	1331152	656301	0	0
T13	537366	265163	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	169971	0	0
T25	68287	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4028071	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	532955	6389	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	172001	0	0	0
T8	21103	832	0	0
T9	4953	0	0	0
T10	1729	0	0	0
T11	143710	832	0	0
T12	1331152	22093	0	0
T13	537366	6945	0	0
T14	481558	4492	0	0
T15	6624	832	0	0
T16	27977	514	0	0
T17	176750	3241	0	0
T19	0	5823	0	0
T20	0	16080	0	0
T21	0	5651	0	0
T23	1185	0	0	0
T24	0	832	0	0
T25	136574	0	0	0
T26	52630	0	0	0
T27	0	5049	0	0
T28	0	18744	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0
T46	0	2997	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4028071	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	532955	6389	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	172001	0	0	0
T8	21103	832	0	0
T9	4953	0	0	0
T10	1729	0	0	0
T11	143710	832	0	0
T12	1331152	22093	0	0
T13	537366	6945	0	0
T14	481558	4492	0	0
T15	6624	832	0	0
T16	27977	514	0	0
T17	176750	3241	0	0
T19	0	5823	0	0
T20	0	16080	0	0
T21	0	5651	0	0
T23	1185	0	0	0
T24	0	832	0	0
T25	136574	0	0	0
T26	52630	0	0	0
T27	0	5049	0	0
T28	0	18744	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0
T46	0	2997	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4028071	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	532955	6389	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	172001	0	0	0
T8	21103	832	0	0
T9	4953	0	0	0
T10	1729	0	0	0
T11	143710	832	0	0
T12	1331152	22093	0	0
T13	537366	6945	0	0
T14	481558	4492	0	0
T15	6624	832	0	0
T16	27977	514	0	0
T17	176750	3241	0	0
T19	0	5823	0	0
T20	0	16080	0	0
T21	0	5651	0	0
T23	1185	0	0	0
T24	0	832	0	0
T25	136574	0	0	0
T26	52630	0	0	0
T27	0	5049	0	0
T28	0	18744	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0
T46	0	2997	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4028071	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	532955	6389	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	172001	0	0	0
T8	21103	832	0	0
T9	4953	0	0	0
T10	1729	0	0	0
T11	143710	832	0	0
T12	1331152	22093	0	0
T13	537366	6945	0	0
T14	481558	4492	0	0
T15	6624	832	0	0
T16	27977	514	0	0
T17	176750	3241	0	0
T19	0	5823	0	0
T20	0	16080	0	0
T21	0	5651	0	0
T23	1185	0	0	0
T24	0	832	0	0
T25	136574	0	0	0
T26	52630	0	0	0
T27	0	5049	0	0
T28	0	18744	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0
T46	0	2997	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4	0	976
T34	177393	1	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	443544	0	0	1
T55	21448	0	0	1
T56	84664	0	0	1
T57	167764	0	0	1
T58	191424	0	0	1
T59	112884	0	0	1
T60	2049	0	0	1
T61	128265	0	0	1
T62	105036	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	660404243	0	0
T1	88485	86095	0	0
T2	86348	50745	0	0
T3	11326	7559	0	0
T4	640760	529392	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	294678	162268	0	0
T8	23655	21034	0	0
T9	5313	4883	0	0
T10	1729	1652	0	0
T11	287420	143710	0	0
T12	1331152	656301	0	0
T13	537366	265163	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	169971	0	0
T25	68287	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	822574582	4028071	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	532955	6389	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	172001	0	0	0
T8	21103	832	0	0
T9	4953	0	0	0
T10	1729	0	0	0
T11	143710	832	0	0
T12	1331152	22093	0	0
T13	537366	6945	0	0
T14	481558	4492	0	0
T15	6624	832	0	0
T16	27977	514	0	0
T17	176750	3241	0	0
T19	0	5823	0	0
T20	0	16080	0	0
T21	0	5651	0	0
T23	1185	0	0	0
T24	0	832	0	0
T25	136574	0	0	0
T26	52630	0	0	0
T27	0	5049	0	0
T28	0	18744	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0
T46	0	2997	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Unreachable
1	1	Covered	T4,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	160586126	28350791	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	160586126	692715	0	0
GntImpliesValid_A	160586126	692715	0	0
GrantKnown_A	160586126	28350791	0	0
IdxKnown_A	160586126	28350791	0	0
IndexIsCorrect_A	160586126	692715	0	0
LockArbDecision_A	160586126	0	0	0
NoReadyValidNoGrant_A	160586126	0	0	0
ReadyAndValidImplyGrant_A	160586126	692715	0	0
ReqAndReadyImplyGrant_A	160586126	692715	0	0
ReqImpliesValid_A	160586126	692715	0	0
ReqStaysHighUntilGranted0_M	160586126	0	0	0
RoundRobin_A	160586126	0	0	0
ValidKnown_A	160586126	28350791	0	0
gen_data_port_assertion.DataFlow_A	160586126	692715	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	28350791	0	0
T1	49819	47520	0	0
T2	35506	0	0	0
T3	3712	0	0	0
T4	107805	104312	0	0
T7	122677	113032	0	0
T8	2552	0	0	0
T9	360	360	0	0
T11	143710	0	0	0
T12	665576	236952	0	0
T13	268683	23352	0	0
T17	0	112616	0	0
T25	0	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	692715	0	0
T4	107805	4229	0	0
T7	122677	0	0	0
T8	2552	0	0	0
T9	360	0	0	0
T11	143710	0	0	0
T12	665576	4657	0	0
T13	268683	1113	0	0
T14	240779	0	0	0
T15	3312	0	0	0
T17	0	3028	0	0
T19	0	4659	0	0
T20	0	10061	0	0
T21	0	5651	0	0
T25	68287	0	0	0
T27	0	5049	0	0
T28	0	5234	0	0
T46	0	2997	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	692715	0	0
T4	107805	4229	0	0
T7	122677	0	0	0
T8	2552	0	0	0
T9	360	0	0	0
T11	143710	0	0	0
T12	665576	4657	0	0
T13	268683	1113	0	0
T14	240779	0	0	0
T15	3312	0	0	0
T17	0	3028	0	0
T19	0	4659	0	0
T20	0	10061	0	0
T21	0	5651	0	0
T25	68287	0	0	0
T27	0	5049	0	0
T28	0	5234	0	0
T46	0	2997	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	28350791	0	0
T1	49819	47520	0	0
T2	35506	0	0	0
T3	3712	0	0	0
T4	107805	104312	0	0
T7	122677	113032	0	0
T8	2552	0	0	0
T9	360	360	0	0
T11	143710	0	0	0
T12	665576	236952	0	0
T13	268683	23352	0	0
T17	0	112616	0	0
T25	0	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	28350791	0	0
T1	49819	47520	0	0
T2	35506	0	0	0
T3	3712	0	0	0
T4	107805	104312	0	0
T7	122677	113032	0	0
T8	2552	0	0	0
T9	360	360	0	0
T11	143710	0	0	0
T12	665576	236952	0	0
T13	268683	23352	0	0
T17	0	112616	0	0
T25	0	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	692715	0	0
T4	107805	4229	0	0
T7	122677	0	0	0
T8	2552	0	0	0
T9	360	0	0	0
T11	143710	0	0	0
T12	665576	4657	0	0
T13	268683	1113	0	0
T14	240779	0	0	0
T15	3312	0	0	0
T17	0	3028	0	0
T19	0	4659	0	0
T20	0	10061	0	0
T21	0	5651	0	0
T25	68287	0	0	0
T27	0	5049	0	0
T28	0	5234	0	0
T46	0	2997	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	692715	0	0
T4	107805	4229	0	0
T7	122677	0	0	0
T8	2552	0	0	0
T9	360	0	0	0
T11	143710	0	0	0
T12	665576	4657	0	0
T13	268683	1113	0	0
T14	240779	0	0	0
T15	3312	0	0	0
T17	0	3028	0	0
T19	0	4659	0	0
T20	0	10061	0	0
T21	0	5651	0	0
T25	68287	0	0	0
T27	0	5049	0	0
T28	0	5234	0	0
T46	0	2997	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	692715	0	0
T4	107805	4229	0	0
T7	122677	0	0	0
T8	2552	0	0	0
T9	360	0	0	0
T11	143710	0	0	0
T12	665576	4657	0	0
T13	268683	1113	0	0
T14	240779	0	0	0
T15	3312	0	0	0
T17	0	3028	0	0
T19	0	4659	0	0
T20	0	10061	0	0
T21	0	5651	0	0
T25	68287	0	0	0
T27	0	5049	0	0
T28	0	5234	0	0
T46	0	2997	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	692715	0	0
T4	107805	4229	0	0
T7	122677	0	0	0
T8	2552	0	0	0
T9	360	0	0	0
T11	143710	0	0	0
T12	665576	4657	0	0
T13	268683	1113	0	0
T14	240779	0	0	0
T15	3312	0	0	0
T17	0	3028	0	0
T19	0	4659	0	0
T20	0	10061	0	0
T21	0	5651	0	0
T25	68287	0	0	0
T27	0	5049	0	0
T28	0	5234	0	0
T46	0	2997	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	28350791	0	0
T1	49819	47520	0	0
T2	35506	0	0	0
T3	3712	0	0	0
T4	107805	104312	0	0
T7	122677	113032	0	0
T8	2552	0	0	0
T9	360	360	0	0
T11	143710	0	0	0
T12	665576	236952	0	0
T13	268683	23352	0	0
T17	0	112616	0	0
T25	0	62688	0	0
T27	0	114768	0	0
T28	0	158920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	692715	0	0
T4	107805	4229	0	0
T7	122677	0	0	0
T8	2552	0	0	0
T9	360	0	0	0
T11	143710	0	0	0
T12	665576	4657	0	0
T13	268683	1113	0	0
T14	240779	0	0	0
T15	3312	0	0	0
T17	0	3028	0	0
T19	0	4659	0	0
T20	0	10061	0	0
T21	0	5651	0	0
T25	68287	0	0	0
T27	0	5049	0	0
T28	0	5234	0	0
T46	0	2997	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T12,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T13,T14
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	160586126	130741761	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	160586126	903286	0	0
GntImpliesValid_A	160586126	903286	0	0
GrantKnown_A	160586126	130741761	0	0
IdxKnown_A	160586126	130741761	0	0
IndexIsCorrect_A	160586126	903286	0	0
LockArbDecision_A	160586126	0	0	0
NoReadyValidNoGrant_A	160586126	0	0	0
ReadyAndValidImplyGrant_A	160586126	903286	0	0
ReqAndReadyImplyGrant_A	160586126	903286	0	0
ReqImpliesValid_A	160586126	903286	0	0
ReqStaysHighUntilGranted0_M	160586126	0	0	0
RoundRobin_A	160586126	0	0	0
ValidKnown_A	160586126	130741761	0	0
gen_data_port_assertion.DataFlow_A	160586126	903286	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	130741761	0	0
T2	35506	35506	0	0
T3	3712	3712	0	0
T4	107805	0	0	0
T7	122677	0	0	0
T8	2552	2552	0	0
T9	360	0	0	0
T11	143710	143710	0	0
T12	665576	419349	0	0
T13	268683	241811	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	57355	0	0
T25	68287	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	903286	0	0
T12	665576	2970	0	0
T13	268683	266	0	0
T14	240779	262	0	0
T15	3312	0	0	0
T16	27977	514	0	0
T17	176750	213	0	0
T19	0	1164	0	0
T20	0	6019	0	0
T25	68287	0	0	0
T26	52630	0	0	0
T28	0	13510	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	903286	0	0
T12	665576	2970	0	0
T13	268683	266	0	0
T14	240779	262	0	0
T15	3312	0	0	0
T16	27977	514	0	0
T17	176750	213	0	0
T19	0	1164	0	0
T20	0	6019	0	0
T25	68287	0	0	0
T26	52630	0	0	0
T28	0	13510	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	130741761	0	0
T2	35506	35506	0	0
T3	3712	3712	0	0
T4	107805	0	0	0
T7	122677	0	0	0
T8	2552	2552	0	0
T9	360	0	0	0
T11	143710	143710	0	0
T12	665576	419349	0	0
T13	268683	241811	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	57355	0	0
T25	68287	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	130741761	0	0
T2	35506	35506	0	0
T3	3712	3712	0	0
T4	107805	0	0	0
T7	122677	0	0	0
T8	2552	2552	0	0
T9	360	0	0	0
T11	143710	143710	0	0
T12	665576	419349	0	0
T13	268683	241811	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	57355	0	0
T25	68287	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	903286	0	0
T12	665576	2970	0	0
T13	268683	266	0	0
T14	240779	262	0	0
T15	3312	0	0	0
T16	27977	514	0	0
T17	176750	213	0	0
T19	0	1164	0	0
T20	0	6019	0	0
T25	68287	0	0	0
T26	52630	0	0	0
T28	0	13510	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	903286	0	0
T12	665576	2970	0	0
T13	268683	266	0	0
T14	240779	262	0	0
T15	3312	0	0	0
T16	27977	514	0	0
T17	176750	213	0	0
T19	0	1164	0	0
T20	0	6019	0	0
T25	68287	0	0	0
T26	52630	0	0	0
T28	0	13510	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	903286	0	0
T12	665576	2970	0	0
T13	268683	266	0	0
T14	240779	262	0	0
T15	3312	0	0	0
T16	27977	514	0	0
T17	176750	213	0	0
T19	0	1164	0	0
T20	0	6019	0	0
T25	68287	0	0	0
T26	52630	0	0	0
T28	0	13510	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	903286	0	0
T12	665576	2970	0	0
T13	268683	266	0	0
T14	240779	262	0	0
T15	3312	0	0	0
T16	27977	514	0	0
T17	176750	213	0	0
T19	0	1164	0	0
T20	0	6019	0	0
T25	68287	0	0	0
T26	52630	0	0	0
T28	0	13510	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	130741761	0	0
T2	35506	35506	0	0
T3	3712	3712	0	0
T4	107805	0	0	0
T7	122677	0	0	0
T8	2552	2552	0	0
T9	360	0	0	0
T11	143710	143710	0	0
T12	665576	419349	0	0
T13	268683	241811	0	0
T14	0	239116	0	0
T15	0	3312	0	0
T16	0	27568	0	0
T17	0	57355	0	0
T25	68287	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160586126	903286	0	0
T12	665576	2970	0	0
T13	268683	266	0	0
T14	240779	262	0	0
T15	3312	0	0	0
T16	27977	514	0	0
T17	176750	213	0	0
T19	0	1164	0	0
T20	0	6019	0	0
T25	68287	0	0	0
T26	52630	0	0	0
T28	0	13510	0	0
T32	473	0	0	0
T39	0	700	0	0
T40	0	2356	0	0
T43	4032	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	501402330	501311691	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	501402330	2432070	0	0
GntImpliesValid_A	501402330	2432070	0	0
GrantKnown_A	501402330	501311691	0	0
IdxKnown_A	501402330	501311691	0	0
IndexIsCorrect_A	501402330	2432070	0	0
LockArbDecision_A	501402330	0	0	0
NoReadyValidNoGrant_A	501402330	0	0	0
ReadyAndValidImplyGrant_A	501402330	2432070	0	0
ReqAndReadyImplyGrant_A	501402330	2432070	0	0
ReqImpliesValid_A	501402330	2432070	0	0
ReqStaysHighUntilGranted0_M	501402330	0	0	0
RoundRobin_A	501402330	4	0	976
ValidKnown_A	501402330	501311691	0	0
gen_data_port_assertion.DataFlow_A	501402330	2432070	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	501311691	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	2432070	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	2160	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	832	0	0
T12	0	14466	0	0
T13	0	5566	0	0
T14	0	4230	0	0
T15	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	2432070	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	2160	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	832	0	0
T12	0	14466	0	0
T13	0	5566	0	0
T14	0	4230	0	0
T15	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	501311691	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	501311691	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	2432070	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	2160	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	832	0	0
T12	0	14466	0	0
T13	0	5566	0	0
T14	0	4230	0	0
T15	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	2432070	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	2160	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	832	0	0
T12	0	14466	0	0
T13	0	5566	0	0
T14	0	4230	0	0
T15	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	2432070	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	2160	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	832	0	0
T12	0	14466	0	0
T13	0	5566	0	0
T14	0	4230	0	0
T15	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	2432070	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	2160	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	832	0	0
T12	0	14466	0	0
T13	0	5566	0	0
T14	0	4230	0	0
T15	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	4	0	976
T34	177393	1	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	443544	0	0	1
T55	21448	0	0	1
T56	84664	0	0	1
T57	167764	0	0	1
T58	191424	0	0	1
T59	112884	0	0	1
T60	2049	0	0	1
T61	128265	0	0	1
T62	105036	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	501311691	0	0
T1	38666	38575	0	0
T2	15336	15239	0	0
T3	3902	3847	0	0
T4	425150	425080	0	0
T5	1263	1172	0	0
T6	793	725	0	0
T7	49324	49236	0	0
T8	18551	18482	0	0
T9	4593	4523	0	0
T10	1729	1652	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501402330	2432070	0	0
T2	15336	832	0	0
T3	3902	832	0	0
T4	425150	2160	0	0
T5	1263	0	0	0
T6	793	0	0	0
T7	49324	0	0	0
T8	18551	832	0	0
T9	4593	0	0	0
T10	1729	0	0	0
T11	0	832	0	0
T12	0	14466	0	0
T13	0	5566	0	0
T14	0	4230	0	0
T15	0	832	0	0
T23	1185	0	0	0
T24	0	832	0	0