Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3766854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4403901

1

T1

2

T2

2008

T3

36822

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4473264	1			T1	1		T2	4578		T3	56056
values[0x0]	1847675	1			T1	1		T2	975		T3	19016
values[0x1]	1849816	1			T2	1015		T3	18783		T4	835

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2665422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5505333

1

T1

2

T2

3446

T3

54700

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32250	1			T2	10		T3	356		T4	14
valid_sources[0x01]	30834	1			T2	34		T3	363		T4	21
valid_sources[0x02]	29144	1			T2	17		T3	333		T4	25
valid_sources[0x03]	33678	1			T2	38		T3	370		T4	6
valid_sources[0x04]	30357	1			T2	55		T3	349		T4	16
valid_sources[0x05]	31265	1			T2	33		T3	371		T4	19
valid_sources[0x06]	30356	1			T2	23		T3	325		T4	11
valid_sources[0x07]	32764	1			T2	26		T3	351		T4	18
valid_sources[0x08]	31229	1			T2	2		T3	365		T4	30
valid_sources[0x09]	29046	1			T2	47		T3	364		T4	25
valid_sources[0x0a]	30468	1			T2	2		T3	394		T4	17
valid_sources[0x0b]	30095	1			T2	4		T3	335		T4	29
valid_sources[0x0c]	29628	1			T2	41		T3	383		T4	21
valid_sources[0x0d]	31211	1			T2	2		T3	347		T4	14
valid_sources[0x0e]	32364	1			T2	17		T3	366		T4	22
valid_sources[0x0f]	28839	1			T2	22		T3	316		T4	16
valid_sources[0x10]	28471	1			T2	12		T3	352		T4	14
valid_sources[0x11]	33827	1			T2	17		T3	386		T4	12
valid_sources[0x12]	31376	1			T2	37		T3	368		T4	21
valid_sources[0x13]	28132	1			T2	11		T3	376		T4	16
valid_sources[0x14]	31631	1			T2	23		T3	403		T4	21
valid_sources[0x15]	28367	1			T2	2		T3	344		T4	14
valid_sources[0x16]	27923	1			T2	20		T3	367		T4	8
valid_sources[0x17]	35078	1			T2	47		T3	377		T4	17
valid_sources[0x18]	32731	1			T2	27		T3	389		T4	21
valid_sources[0x19]	27833	1			T2	5		T3	387		T4	15
valid_sources[0x1a]	29604	1			T2	33		T3	351		T4	20
valid_sources[0x1b]	30237	1			T2	24		T3	366		T4	18
valid_sources[0x1c]	37603	1			T2	12		T3	351		T4	20
valid_sources[0x1d]	47002	1			T2	30		T3	344		T4	16
valid_sources[0x1e]	31605	1			T2	24		T3	375		T4	23
valid_sources[0x1f]	31000	1			T2	55		T3	369		T4	15
valid_sources[0x20]	29117	1			T2	4		T3	364		T4	18
valid_sources[0x21]	32828	1			T2	21		T3	362		T4	19
valid_sources[0x22]	35499	1			T2	41		T3	377		T4	17
valid_sources[0x23]	28843	1			T2	12		T3	377		T4	20
valid_sources[0x24]	30243	1			T2	32		T3	417		T4	22
valid_sources[0x25]	30017	1			T2	43		T3	372		T4	20
valid_sources[0x26]	32670	1			T2	15		T3	347		T4	9
valid_sources[0x27]	35973	1			T2	38		T3	337		T4	18
valid_sources[0x28]	54666	1			T2	50		T3	350		T4	15
valid_sources[0x29]	29715	1			T2	7		T3	362		T4	14
valid_sources[0x2a]	30428	1			T2	26		T3	355		T4	21
valid_sources[0x2b]	33220	1			T2	26		T3	410		T4	17
valid_sources[0x2c]	33519	1			T2	22		T3	343		T4	20
valid_sources[0x2d]	35496	1			T2	31		T3	352		T4	11
valid_sources[0x2e]	33991	1			T2	4		T3	409		T4	18
valid_sources[0x2f]	27527	1			T2	25		T3	347		T4	20
valid_sources[0x30]	30923	1			T2	23		T3	406		T4	22
valid_sources[0x31]	30688	1			T2	45		T3	368		T4	23
valid_sources[0x32]	40403	1			T2	41		T3	363		T4	16
valid_sources[0x33]	28289	1			T2	9		T3	390		T4	12
valid_sources[0x34]	32299	1			T2	8		T3	334		T4	16
valid_sources[0x35]	29719	1			T2	11		T3	390		T4	18
valid_sources[0x36]	34624	1			T2	4		T3	370		T4	18
valid_sources[0x37]	30085	1			T2	8		T3	364		T4	19
valid_sources[0x38]	32815	1			T2	18		T3	377		T4	27
valid_sources[0x39]	30802	1			T2	53		T3	356		T4	16
valid_sources[0x3a]	31166	1			T1	2		T2	12		T3	339
valid_sources[0x3b]	30406	1			T2	7		T3	371		T4	14
valid_sources[0x3c]	28793	1			T2	38		T3	384		T4	9
valid_sources[0x3d]	43449	1			T2	28		T3	402		T4	19
valid_sources[0x3e]	32358	1			T2	1		T3	372		T4	23
valid_sources[0x3f]	32758	1			T2	29		T3	388		T4	13
valid_sources[0x40]	31768	1			T2	7		T3	377		T4	16
valid_sources[0x41]	28888	1			T2	76		T3	381		T4	16
valid_sources[0x42]	31362	1			T2	7		T3	375		T4	17
valid_sources[0x43]	29150	1			T2	1		T3	399		T4	18
valid_sources[0x44]	27127	1			T2	24		T3	376		T4	17
valid_sources[0x45]	32143	1			T2	83		T3	344		T4	26
valid_sources[0x46]	32556	1			T2	8		T3	387		T4	15
valid_sources[0x47]	32071	1			T2	26		T3	342		T4	20
valid_sources[0x48]	36978	1			T2	21		T3	335		T4	15
valid_sources[0x49]	34188	1			T2	57		T3	385		T4	17
valid_sources[0x4a]	30861	1			T2	4		T3	382		T4	24
valid_sources[0x4b]	35118	1			T2	30		T3	369		T4	21
valid_sources[0x4c]	33328	1			T2	45		T3	363		T4	20
valid_sources[0x4d]	31596	1			T2	25		T3	393		T4	19
valid_sources[0x4e]	26789	1			T2	37		T3	336		T4	19
valid_sources[0x4f]	30203	1			T2	25		T3	371		T4	13
valid_sources[0x50]	27624	1			T2	45		T3	312		T4	17
valid_sources[0x51]	31842	1			T2	17		T3	351		T4	21
valid_sources[0x52]	37417	1			T2	32		T3	391		T4	12
valid_sources[0x53]	30273	1			T2	76		T3	386		T4	12
valid_sources[0x54]	31334	1			T2	15		T3	346		T4	12
valid_sources[0x55]	32073	1			T2	23		T3	375		T4	18
valid_sources[0x56]	35694	1			T2	42		T3	382		T4	19
valid_sources[0x57]	30588	1			T2	37		T3	375		T4	14
valid_sources[0x58]	31998	1			T2	62		T3	390		T4	19
valid_sources[0x59]	29691	1			T2	17		T3	380		T4	22
valid_sources[0x5a]	29426	1			T2	3		T3	358		T4	25
valid_sources[0x5b]	30805	1			T2	25		T3	342		T4	21
valid_sources[0x5c]	27757	1			T2	36		T3	362		T4	9
valid_sources[0x5d]	29683	1			T2	14		T3	372		T4	19
valid_sources[0x5e]	35331	1			T2	41		T3	362		T4	21
valid_sources[0x5f]	28953	1			T2	82		T3	409		T4	21
valid_sources[0x60]	31804	1			T2	14		T3	347		T4	19
valid_sources[0x61]	32659	1			T2	6		T3	378		T4	17
valid_sources[0x62]	29408	1			T2	16		T3	361		T4	20
valid_sources[0x63]	32272	1			T2	27		T3	411		T4	20
valid_sources[0x64]	36947	1			T2	70		T3	341		T4	25
valid_sources[0x65]	30862	1			T2	24		T3	360		T4	12
valid_sources[0x66]	35999	1			T2	41		T3	350		T4	22
valid_sources[0x67]	32592	1			T2	28		T3	349		T4	22
valid_sources[0x68]	27522	1			T2	10		T3	370		T4	18
valid_sources[0x69]	32454	1			T2	21		T3	373		T4	19
valid_sources[0x6a]	28303	1			T2	10		T3	327		T4	13
valid_sources[0x6b]	29382	1			T2	4		T3	324		T4	19
valid_sources[0x6c]	29107	1			T2	20		T3	373		T4	19
valid_sources[0x6d]	33682	1			T2	52		T3	373		T4	24
valid_sources[0x6e]	29040	1			T2	38		T3	369		T4	18
valid_sources[0x6f]	30917	1			T2	30		T3	419		T4	18
valid_sources[0x70]	29335	1			T2	31		T3	318		T4	12
valid_sources[0x71]	40856	1			T2	24		T3	397		T4	18
valid_sources[0x72]	32949	1			T2	29		T3	370		T4	14
valid_sources[0x73]	36775	1			T2	44		T3	352		T4	14
valid_sources[0x74]	34315	1			T2	24		T3	365		T4	17
valid_sources[0x75]	27366	1			T2	7		T3	369		T4	16
valid_sources[0x76]	29621	1			T2	26		T3	356		T4	20
valid_sources[0x77]	31517	1			T2	101		T3	376		T4	16
valid_sources[0x78]	29856	1			T2	61		T3	361		T4	19
valid_sources[0x79]	30231	1			T2	2		T3	343		T4	16
valid_sources[0x7a]	29429	1			T2	49		T3	360		T4	23
valid_sources[0x7b]	33324	1			T2	14		T3	363		T4	23
valid_sources[0x7c]	27152	1			T2	46		T3	397		T4	17
valid_sources[0x7d]	29935	1			T2	52		T3	388		T4	19
valid_sources[0x7e]	35128	1			T2	41		T3	385		T4	14
valid_sources[0x7f]	31245	1			T2	6		T3	372		T4	20
valid_sources[0x80]	30830	1			T2	12		T3	347		T4	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1056770

1

T1

1

T2

573

T3

4450

values[0x0]

all_enables

biggest_size

1685456

1

T1

1

T2

713

T3

16416

values[0x1]

all_enables

biggest_size

1661675

1

T2

722

T3

15956

T4

827