Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3788232

1

T2

4560

T3

57033

T4

1523

full_word

4403038

1

T1

2

T2

2008

T3

36822

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8190840	1			T1	2		T2	6568		T3	93855
auto[TlIntgErrCmd]	136	1			T96	10		T99	6		T100	7
auto[TlIntgErrData]	149	1			T96	7		T99	11		T100	2
auto[TlIntgErrBoth]	145	1			T96	13		T99	13		T100	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4474980

1

T1

1

T2

4578

T3

56056

auto[1]

3716290

1

T1

1

T2

1990

T3

37799

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3417909	1			T2	4005		T3	51606		T4	1511
auto[TlIntgErrNone]	partial	auto[1]	369935	1			T2	555		T3	5427		T4	12
auto[TlIntgErrNone]	full_word	auto[0]	1056886	1			T1	1		T2	573		T3	4450
auto[TlIntgErrNone]	full_word	auto[1]	3346110	1			T1	1		T2	1435		T3	32372
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T96	4		T99	3		T100	4
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T96	4		T99	2		T100	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T176	1		T177	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	13	1			T96	2		T99	1		T100	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T96	4		T99	4		T100	1
auto[TlIntgErrData]	partial	auto[1]	70	1			T96	2		T99	6		T100	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T99	1		T176	1		T179	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T96	1		T176	3		T143	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T96	3		T99	5		T100	1
auto[TlIntgErrBoth]	partial	auto[1]	78	1			T96	9		T99	7		T175	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T178	2		T180	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T96	1		T99	1		T176	1