Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467825371	2954912	0	0
DepthKnown_A	467825371	467690134	0	0
RvalidKnown_A	467825371	467690134	0	0
WreadyKnown_A	467825371	467690134	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	2954912	0	0
T3	454862	14970	0	0
T4	103453	3201	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	1663	0	0
T9	9919	1663	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	5373	1663	0	0
T13	0	2500	0	0
T14	0	20792	0	0
T15	0	11645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467825371	3287592	0	0
DepthKnown_A	467825371	467690134	0	0
RvalidKnown_A	467825371	467690134	0	0
WreadyKnown_A	467825371	467690134	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	3287592	0	0
T3	454862	9984	0	0
T4	103453	1606	0	0
T5	105294	3798	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	5373	832	0	0
T13	0	4694	0	0
T14	0	14144	0	0
T15	0	9152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467825371	201503	0	0
DepthKnown_A	467825371	467690134	0	0
RvalidKnown_A	467825371	467690134	0	0
WreadyKnown_A	467825371	467690134	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	201503	0	0
T2	343406	471	0	0
T3	454862	1313	0	0
T4	103453	0	0	0
T5	105294	0	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	0	0	0
T9	9919	0	0	0
T10	5525	0	0	0
T11	157118	0	0	0
T13	0	65	0	0
T14	0	1344	0	0
T15	0	481	0	0
T23	0	67	0	0
T24	0	1424	0	0
T25	0	25	0	0
T37	0	193	0	0
T38	0	322	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467825371	429414	0	0
DepthKnown_A	467825371	467690134	0	0
RvalidKnown_A	467825371	467690134	0	0
WreadyKnown_A	467825371	467690134	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	429414	0	0
T2	343406	471	0	0
T3	454862	1313	0	0
T4	103453	0	0	0
T5	105294	0	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	0	0	0
T9	9919	0	0	0
T10	5525	0	0	0
T11	157118	0	0	0
T13	0	300	0	0
T14	0	1343	0	0
T15	0	481	0	0
T23	0	67	0	0
T24	0	1422	0	0
T25	0	25	0	0
T37	0	919	0	0
T38	0	322	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467825371	6424372	0	0
DepthKnown_A	467825371	467690134	0	0
RvalidKnown_A	467825371	467690134	0	0
WreadyKnown_A	467825371	467690134	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	6424372	0	0
T1	1143	2	0	0
T2	343406	6116	0	0
T3	454862	83018	0	0
T4	103453	3113	0	0
T5	105294	3059	0	0
T6	1660	45	0	0
T7	1868	81	0	0
T8	31892	1010	0	0
T9	9919	210	0	0
T10	5525	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467825371	13053557	0	0
DepthKnown_A	467825371	467690134	0	0
RvalidKnown_A	467825371	467690134	0	0
WreadyKnown_A	467825371	467690134	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	13053557	0	0
T1	1143	2	0	0
T2	343406	6097	0	0
T3	454862	82558	0	0
T4	103453	13371	0	0
T5	105294	13299	0	0
T6	1660	134	0	0
T7	1868	81	0	0
T8	31892	1010	0	0
T9	9919	796	0	0
T10	5525	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467825371	467690134	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0