Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T14
1	0	Covered	T2,T3,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Unreachable
1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T14
1	0	Covered	T3,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T3,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T13
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	769680648	616123008	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	769680648	3933962	0	0
GntImpliesValid_A	769680648	3933962	0	0
GrantKnown_A	769680648	616123008	0	0
IdxKnown_A	769680648	616123008	0	0
IndexIsCorrect_A	769680648	3933962	0	0
LockArbDecision_A	769680648	0	0	0
NoReadyValidNoGrant_A	769680648	0	0	0
ReadyAndValidImplyGrant_A	769680648	3933962	0	0
ReqAndReadyImplyGrant_A	769680648	3933962	0	0
ReqImpliesValid_A	769680648	3933962	0	0
ReqStaysHighUntilGranted0_M	769680648	0	0	0
RoundRobin_A	769680648	7	0	975
ValidKnown_A	769680648	616123008	0	0
gen_data_port_assertion.DataFlow_A	769680648	3933962	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	616123008	0	0
T1	1143	1045	0	0
T2	413133	409253	0	0
T3	1950694	1192515	0	0
T4	170269	136808	0	0
T5	152590	128888	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	88532	60158	0	0
T9	50975	30387	0	0
T10	7039	6095	0	0
T11	37492	18746	0	0
T12	4456	2228	0	0
T13	253560	126248	0	0
T14	112355	1113547	0	0
T15	0	392114	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	3933962	0	0
T2	413133	3864	0	0
T3	1950694	20528	0	0
T4	170269	1600	0	0
T5	152590	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	88532	832	0	0
T9	50975	832	0	0
T10	7039	0	0	0
T11	194610	832	0	0
T12	4456	832	0	0
T13	253560	1997	0	0
T14	112355	28903	0	0
T15	0	2201	0	0
T23	0	519	0	0
T24	0	9482	0	0
T25	0	109	0	0
T26	0	5181	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0
T48	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	3933962	0	0
T2	413133	3864	0	0
T3	1950694	20528	0	0
T4	170269	1600	0	0
T5	152590	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	88532	832	0	0
T9	50975	832	0	0
T10	7039	0	0	0
T11	194610	832	0	0
T12	4456	832	0	0
T13	253560	1997	0	0
T14	112355	28903	0	0
T15	0	2201	0	0
T23	0	519	0	0
T24	0	9482	0	0
T25	0	109	0	0
T26	0	5181	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0
T48	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	616123008	0	0
T1	1143	1045	0	0
T2	413133	409253	0	0
T3	1950694	1192515	0	0
T4	170269	136808	0	0
T5	152590	128888	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	88532	60158	0	0
T9	50975	30387	0	0
T10	7039	6095	0	0
T11	37492	18746	0	0
T12	4456	2228	0	0
T13	253560	126248	0	0
T14	112355	1113547	0	0
T15	0	392114	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	616123008	0	0
T1	1143	1045	0	0
T2	413133	409253	0	0
T3	1950694	1192515	0	0
T4	170269	136808	0	0
T5	152590	128888	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	88532	60158	0	0
T9	50975	30387	0	0
T10	7039	6095	0	0
T11	37492	18746	0	0
T12	4456	2228	0	0
T13	253560	126248	0	0
T14	112355	1113547	0	0
T15	0	392114	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	3933962	0	0
T2	413133	3864	0	0
T3	1950694	20528	0	0
T4	170269	1600	0	0
T5	152590	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	88532	832	0	0
T9	50975	832	0	0
T10	7039	0	0	0
T11	194610	832	0	0
T12	4456	832	0	0
T13	253560	1997	0	0
T14	112355	28903	0	0
T15	0	2201	0	0
T23	0	519	0	0
T24	0	9482	0	0
T25	0	109	0	0
T26	0	5181	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0
T48	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	3933962	0	0
T2	413133	3864	0	0
T3	1950694	20528	0	0
T4	170269	1600	0	0
T5	152590	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	88532	832	0	0
T9	50975	832	0	0
T10	7039	0	0	0
T11	194610	832	0	0
T12	4456	832	0	0
T13	253560	1997	0	0
T14	112355	28903	0	0
T15	0	2201	0	0
T23	0	519	0	0
T24	0	9482	0	0
T25	0	109	0	0
T26	0	5181	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0
T48	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	3933962	0	0
T2	413133	3864	0	0
T3	1950694	20528	0	0
T4	170269	1600	0	0
T5	152590	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	88532	832	0	0
T9	50975	832	0	0
T10	7039	0	0	0
T11	194610	832	0	0
T12	4456	832	0	0
T13	253560	1997	0	0
T14	112355	28903	0	0
T15	0	2201	0	0
T23	0	519	0	0
T24	0	9482	0	0
T25	0	109	0	0
T26	0	5181	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0
T48	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	3933962	0	0
T2	413133	3864	0	0
T3	1950694	20528	0	0
T4	170269	1600	0	0
T5	152590	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	88532	832	0	0
T9	50975	832	0	0
T10	7039	0	0	0
T11	194610	832	0	0
T12	4456	832	0	0
T13	253560	1997	0	0
T14	112355	28903	0	0
T15	0	2201	0	0
T23	0	519	0	0
T24	0	9482	0	0
T25	0	109	0	0
T26	0	5181	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0
T48	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	7	0	975
T14	507578	1	0	1
T15	284015	0	0	1
T23	21078	0	0	1
T24	382982	0	0	1
T25	2304	0	0	1
T37	214569	0	0	1
T38	527417	0	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	83114	0	0	1
T56	1632	0	0	1
T57	22025	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	616123008	0	0
T1	1143	1045	0	0
T2	413133	409253	0	0
T3	1950694	1192515	0	0
T4	170269	136808	0	0
T5	152590	128888	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	88532	60158	0	0
T9	50975	30387	0	0
T10	7039	6095	0	0
T11	37492	18746	0	0
T12	4456	2228	0	0
T13	253560	126248	0	0
T14	112355	1113547	0	0
T15	0	392114	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769680648	3933962	0	0
T2	413133	3864	0	0
T3	1950694	20528	0	0
T4	170269	1600	0	0
T5	152590	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	88532	832	0	0
T9	50975	832	0	0
T10	7039	0	0	0
T11	194610	832	0	0
T12	4456	832	0	0
T13	253560	1997	0	0
T14	112355	28903	0	0
T15	0	2201	0	0
T23	0	519	0	0
T24	0	9482	0	0
T25	0	109	0	0
T26	0	5181	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0
T48	0	8	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T14
1	0	Covered	T2,T3,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Unreachable
1	1	Covered	T2,T3,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T14
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152042991	28878028	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	152042991	667315	0	0
GntImpliesValid_A	152042991	667315	0	0
GrantKnown_A	152042991	28878028	0	0
IdxKnown_A	152042991	28878028	0	0
IndexIsCorrect_A	152042991	667315	0	0
LockArbDecision_A	152042991	0	0	0
NoReadyValidNoGrant_A	152042991	0	0	0
ReadyAndValidImplyGrant_A	152042991	667315	0	0
ReqAndReadyImplyGrant_A	152042991	667315	0	0
ReqImpliesValid_A	152042991	667315	0	0
ReqStaysHighUntilGranted0_M	152042991	0	0	0
RoundRobin_A	152042991	0	0	0
ValidKnown_A	152042991	28878028	0	0
gen_data_port_assertion.DataFlow_A	152042991	667315	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	28878028	0	0
T2	69727	65944	0	0
T3	747916	148728	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	648	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	339496	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	667315	0	0
T2	69727	2652	0	0
T3	747916	6153	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	4376	0	0
T23	0	519	0	0
T24	0	4283	0	0
T25	0	109	0	0
T26	0	1344	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	667315	0	0
T2	69727	2652	0	0
T3	747916	6153	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	4376	0	0
T23	0	519	0	0
T24	0	4283	0	0
T25	0	109	0	0
T26	0	1344	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	28878028	0	0
T2	69727	65944	0	0
T3	747916	148728	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	648	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	339496	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	28878028	0	0
T2	69727	65944	0	0
T3	747916	148728	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	648	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	339496	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	667315	0	0
T2	69727	2652	0	0
T3	747916	6153	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	4376	0	0
T23	0	519	0	0
T24	0	4283	0	0
T25	0	109	0	0
T26	0	1344	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	667315	0	0
T2	69727	2652	0	0
T3	747916	6153	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	4376	0	0
T23	0	519	0	0
T24	0	4283	0	0
T25	0	109	0	0
T26	0	1344	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	667315	0	0
T2	69727	2652	0	0
T3	747916	6153	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	4376	0	0
T23	0	519	0	0
T24	0	4283	0	0
T25	0	109	0	0
T26	0	1344	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	667315	0	0
T2	69727	2652	0	0
T3	747916	6153	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	4376	0	0
T23	0	519	0	0
T24	0	4283	0	0
T25	0	109	0	0
T26	0	1344	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	28878028	0	0
T2	69727	65944	0	0
T3	747916	148728	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	648	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	339496	0	0
T23	0	35936	0	0
T24	0	304816	0	0
T25	0	2384	0	0
T26	0	33280	0	0
T27	0	90176	0	0
T28	0	90400	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	667315	0	0
T2	69727	2652	0	0
T3	747916	6153	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	0	0	0
T14	0	4376	0	0
T23	0	519	0	0
T24	0	4283	0	0
T25	0	109	0	0
T26	0	1344	0	0
T45	0	352	0	0
T46	0	17	0	0
T47	0	4538	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T14
1	0	Covered	T3,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T3,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T13,T14
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152042991	121738731	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	152042991	905277	0	0
GntImpliesValid_A	152042991	905277	0	0
GrantKnown_A	152042991	121738731	0	0
IdxKnown_A	152042991	121738731	0	0
IndexIsCorrect_A	152042991	905277	0	0
LockArbDecision_A	152042991	0	0	0
NoReadyValidNoGrant_A	152042991	0	0	0
ReadyAndValidImplyGrant_A	152042991	905277	0	0
ReqAndReadyImplyGrant_A	152042991	905277	0	0
ReqImpliesValid_A	152042991	905277	0	0
ReqStaysHighUntilGranted0_M	152042991	0	0	0
RoundRobin_A	152042991	0	0	0
ValidKnown_A	152042991	121738731	0	0
gen_data_port_assertion.DataFlow_A	152042991	905277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	121738731	0	0
T3	747916	588949	0	0
T4	33408	33408	0	0
T5	23648	23648	0	0
T8	28320	28320	0	0
T9	20528	20528	0	0
T10	757	0	0	0
T11	18746	18746	0	0
T12	2228	2228	0	0
T13	126780	126248	0	0
T14	112355	774051	0	0
T15	0	392114	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	905277	0	0
T3	747916	1227	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	264	0	0
T14	112355	7508	0	0
T15	0	2201	0	0
T24	0	5199	0	0
T26	0	3837	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T48	0	8	0	0
T58	0	658	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	905277	0	0
T3	747916	1227	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	264	0	0
T14	112355	7508	0	0
T15	0	2201	0	0
T24	0	5199	0	0
T26	0	3837	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T48	0	8	0	0
T58	0	658	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	121738731	0	0
T3	747916	588949	0	0
T4	33408	33408	0	0
T5	23648	23648	0	0
T8	28320	28320	0	0
T9	20528	20528	0	0
T10	757	0	0	0
T11	18746	18746	0	0
T12	2228	2228	0	0
T13	126780	126248	0	0
T14	112355	774051	0	0
T15	0	392114	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	121738731	0	0
T3	747916	588949	0	0
T4	33408	33408	0	0
T5	23648	23648	0	0
T8	28320	28320	0	0
T9	20528	20528	0	0
T10	757	0	0	0
T11	18746	18746	0	0
T12	2228	2228	0	0
T13	126780	126248	0	0
T14	112355	774051	0	0
T15	0	392114	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	905277	0	0
T3	747916	1227	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	264	0	0
T14	112355	7508	0	0
T15	0	2201	0	0
T24	0	5199	0	0
T26	0	3837	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T48	0	8	0	0
T58	0	658	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	905277	0	0
T3	747916	1227	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	264	0	0
T14	112355	7508	0	0
T15	0	2201	0	0
T24	0	5199	0	0
T26	0	3837	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T48	0	8	0	0
T58	0	658	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	905277	0	0
T3	747916	1227	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	264	0	0
T14	112355	7508	0	0
T15	0	2201	0	0
T24	0	5199	0	0
T26	0	3837	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T48	0	8	0	0
T58	0	658	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	905277	0	0
T3	747916	1227	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	264	0	0
T14	112355	7508	0	0
T15	0	2201	0	0
T24	0	5199	0	0
T26	0	3837	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T48	0	8	0	0
T58	0	658	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	121738731	0	0
T3	747916	588949	0	0
T4	33408	33408	0	0
T5	23648	23648	0	0
T8	28320	28320	0	0
T9	20528	20528	0	0
T10	757	0	0	0
T11	18746	18746	0	0
T12	2228	2228	0	0
T13	126780	126248	0	0
T14	112355	774051	0	0
T15	0	392114	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152042991	905277	0	0
T3	747916	1227	0	0
T4	33408	0	0	0
T5	23648	0	0	0
T8	28320	0	0	0
T9	20528	0	0	0
T10	757	0	0	0
T11	18746	0	0	0
T12	2228	0	0	0
T13	126780	264	0	0
T14	112355	7508	0	0
T15	0	2201	0	0
T24	0	5199	0	0
T26	0	3837	0	0
T37	0	1791	0	0
T38	0	7348	0	0
T48	0	8	0	0
T58	0	658	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T13
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465594666	465506249	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	465594666	2361370	0	0
GntImpliesValid_A	465594666	2361370	0	0
GrantKnown_A	465594666	465506249	0	0
IdxKnown_A	465594666	465506249	0	0
IndexIsCorrect_A	465594666	2361370	0	0
LockArbDecision_A	465594666	0	0	0
NoReadyValidNoGrant_A	465594666	0	0	0
ReadyAndValidImplyGrant_A	465594666	2361370	0	0
ReqAndReadyImplyGrant_A	465594666	2361370	0	0
ReqImpliesValid_A	465594666	2361370	0	0
ReqStaysHighUntilGranted0_M	465594666	0	0	0
RoundRobin_A	465594666	7	0	975
ValidKnown_A	465594666	465506249	0	0
gen_data_port_assertion.DataFlow_A	465594666	2361370	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	465506249	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	2361370	0	0
T2	343406	1212	0	0
T3	454862	13148	0	0
T4	103453	1600	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	0	832	0	0
T13	0	1733	0	0
T14	0	17019	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	2361370	0	0
T2	343406	1212	0	0
T3	454862	13148	0	0
T4	103453	1600	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	0	832	0	0
T13	0	1733	0	0
T14	0	17019	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	465506249	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	465506249	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	2361370	0	0
T2	343406	1212	0	0
T3	454862	13148	0	0
T4	103453	1600	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	0	832	0	0
T13	0	1733	0	0
T14	0	17019	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	2361370	0	0
T2	343406	1212	0	0
T3	454862	13148	0	0
T4	103453	1600	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	0	832	0	0
T13	0	1733	0	0
T14	0	17019	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	2361370	0	0
T2	343406	1212	0	0
T3	454862	13148	0	0
T4	103453	1600	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	0	832	0	0
T13	0	1733	0	0
T14	0	17019	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	2361370	0	0
T2	343406	1212	0	0
T3	454862	13148	0	0
T4	103453	1600	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	0	832	0	0
T13	0	1733	0	0
T14	0	17019	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	7	0	975
T14	507578	1	0	1
T15	284015	0	0	1
T23	21078	0	0	1
T24	382982	0	0	1
T25	2304	0	0	1
T37	214569	0	0	1
T38	527417	0	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	83114	0	0	1
T56	1632	0	0	1
T57	22025	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	465506249	0	0
T1	1143	1045	0	0
T2	343406	343309	0	0
T3	454862	454838	0	0
T4	103453	103400	0	0
T5	105294	105240	0	0
T6	1660	1580	0	0
T7	1868	1776	0	0
T8	31892	31838	0	0
T9	9919	9859	0	0
T10	5525	5447	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465594666	2361370	0	0
T2	343406	1212	0	0
T3	454862	13148	0	0
T4	103453	1600	0	0
T5	105294	832	0	0
T6	1660	0	0	0
T7	1868	0	0	0
T8	31892	832	0	0
T9	9919	832	0	0
T10	5525	0	0	0
T11	157118	832	0	0
T12	0	832	0	0
T13	0	1733	0	0
T14	0	17019	0	0