Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3600557	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4217901

1

T1

876

T2

895

T3

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4377129	1			T1	2		T2	5		T3	152
values[0x0]	1720140	1			T1	433		T2	458		T3	43
values[0x1]	1721189	1			T1	442		T2	438		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2560482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5257976

1

T1

876

T2

895

T3

100

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30463	1			T4	5		T5	61		T6	407
valid_sources[0x01]	31487	1			T5	113		T6	418		T7	28
valid_sources[0x02]	28755	1			T4	20		T5	49		T6	419
valid_sources[0x03]	28760	1			T4	1		T5	23		T6	442
valid_sources[0x04]	29637	1			T4	8		T5	118		T6	425
valid_sources[0x05]	27480	1			T4	19		T5	43		T6	417
valid_sources[0x06]	28480	1			T4	23		T5	64		T6	422
valid_sources[0x07]	30034	1			T4	16		T5	36		T6	429
valid_sources[0x08]	30519	1			T4	23		T5	51		T6	400
valid_sources[0x09]	29188	1			T4	2		T5	56		T6	407
valid_sources[0x0a]	27465	1			T4	5		T5	62		T6	397
valid_sources[0x0b]	30452	1			T4	6		T5	88		T6	411
valid_sources[0x0c]	31547	1			T4	8		T5	23		T6	402
valid_sources[0x0d]	28492	1			T4	2		T5	97		T6	435
valid_sources[0x0e]	27237	1			T4	14		T5	45		T6	395
valid_sources[0x0f]	28524	1			T4	6		T5	21		T6	439
valid_sources[0x10]	30297	1			T4	15		T5	64		T6	451
valid_sources[0x11]	33048	1			T4	11		T5	96		T6	408
valid_sources[0x12]	32417	1			T5	45		T6	403		T7	52
valid_sources[0x13]	29949	1			T4	6		T5	45		T6	382
valid_sources[0x14]	43349	1			T4	5		T5	34		T6	436
valid_sources[0x15]	29601	1			T4	9		T5	116		T6	387
valid_sources[0x16]	26714	1			T4	17		T5	13		T6	379
valid_sources[0x17]	29668	1			T4	6		T5	117		T6	432
valid_sources[0x18]	31045	1			T4	4		T5	92		T6	403
valid_sources[0x19]	34233	1			T4	9		T5	55		T6	454
valid_sources[0x1a]	29259	1			T4	13		T5	17		T6	411
valid_sources[0x1b]	36454	1			T4	1		T5	7		T6	375
valid_sources[0x1c]	31013	1			T4	5		T5	58		T6	448
valid_sources[0x1d]	29029	1			T4	1		T5	50		T6	407
valid_sources[0x1e]	29498	1			T4	16		T5	19		T6	453
valid_sources[0x1f]	29833	1			T4	5		T5	21		T6	438
valid_sources[0x20]	30431	1			T4	10		T5	15		T6	416
valid_sources[0x21]	28615	1			T4	1		T5	83		T6	477
valid_sources[0x22]	28964	1			T4	12		T5	22		T6	388
valid_sources[0x23]	28637	1			T4	19		T5	35		T6	443
valid_sources[0x24]	29962	1			T4	1		T5	83		T6	408
valid_sources[0x25]	31047	1			T5	74		T6	454		T7	74
valid_sources[0x26]	46720	1			T4	8		T5	41		T6	419
valid_sources[0x27]	27976	1			T4	21		T5	42		T6	402
valid_sources[0x28]	30818	1			T4	2		T5	82		T6	447
valid_sources[0x29]	39634	1			T4	7		T5	34		T6	351
valid_sources[0x2a]	26493	1			T4	4		T5	80		T6	447
valid_sources[0x2b]	30140	1			T4	14		T5	71		T6	419
valid_sources[0x2c]	30334	1			T4	5		T5	83		T6	401
valid_sources[0x2d]	31168	1			T4	1		T5	114		T6	411
valid_sources[0x2e]	30792	1			T5	97		T6	447		T7	65
valid_sources[0x2f]	28516	1			T5	75		T6	442		T7	56
valid_sources[0x30]	29796	1			T4	2		T5	53		T6	470
valid_sources[0x31]	30052	1			T4	2		T5	27		T6	474
valid_sources[0x32]	30318	1			T4	1		T5	89		T6	346
valid_sources[0x33]	29085	1			T4	2		T5	8		T6	387
valid_sources[0x34]	29771	1			T1	877		T4	12		T5	67
valid_sources[0x35]	34499	1			T5	45		T6	431		T7	105
valid_sources[0x36]	33642	1			T4	10		T5	58		T6	390
valid_sources[0x37]	27797	1			T4	1		T5	40		T6	440
valid_sources[0x38]	28946	1			T4	5		T5	56		T6	393
valid_sources[0x39]	28641	1			T4	18		T5	36		T6	409
valid_sources[0x3a]	29630	1			T4	1		T5	87		T6	419
valid_sources[0x3b]	28698	1			T4	8		T5	23		T6	389
valid_sources[0x3c]	29203	1			T4	8		T5	136		T6	410
valid_sources[0x3d]	30660	1			T4	5		T5	12		T6	417
valid_sources[0x3e]	29507	1			T4	28		T5	27		T6	467
valid_sources[0x3f]	27760	1			T5	33		T6	401		T7	25
valid_sources[0x40]	29669	1			T4	26		T5	96		T6	432
valid_sources[0x41]	32422	1			T4	13		T5	76		T6	391
valid_sources[0x42]	28883	1			T4	9		T5	104		T6	370
valid_sources[0x43]	28379	1			T4	14		T5	26		T6	460
valid_sources[0x44]	28412	1			T4	5		T5	39		T6	407
valid_sources[0x45]	32813	1			T4	14		T5	40		T6	405
valid_sources[0x46]	33130	1			T4	7		T5	24		T6	476
valid_sources[0x47]	27087	1			T4	11		T5	57		T6	442
valid_sources[0x48]	26766	1			T4	1		T5	23		T6	427
valid_sources[0x49]	32117	1			T5	29		T6	464		T7	17
valid_sources[0x4a]	28680	1			T4	9		T5	22		T6	446
valid_sources[0x4b]	29097	1			T4	7		T5	2		T6	413
valid_sources[0x4c]	34249	1			T5	39		T6	431		T7	73
valid_sources[0x4d]	32683	1			T4	7		T5	90		T6	442
valid_sources[0x4e]	29201	1			T4	17		T5	82		T6	400
valid_sources[0x4f]	30273	1			T4	2		T5	114		T6	446
valid_sources[0x50]	33662	1			T4	2		T5	126		T6	426
valid_sources[0x51]	53791	1			T4	6		T5	29		T6	442
valid_sources[0x52]	28136	1			T4	1		T5	44		T6	428
valid_sources[0x53]	28647	1			T4	10		T5	73		T6	407
valid_sources[0x54]	30709	1			T4	8		T5	47		T6	437
valid_sources[0x55]	27574	1			T4	9		T5	54		T6	467
valid_sources[0x56]	29331	1			T4	7		T5	34		T6	446
valid_sources[0x57]	28193	1			T4	24		T5	40		T6	386
valid_sources[0x58]	33813	1			T4	1		T5	5		T6	381
valid_sources[0x59]	30460	1			T4	11		T5	69		T6	438
valid_sources[0x5a]	28439	1			T4	8		T5	25		T6	408
valid_sources[0x5b]	29476	1			T4	12		T5	28		T6	391
valid_sources[0x5c]	29725	1			T4	5		T5	71		T6	445
valid_sources[0x5d]	32000	1			T4	7		T5	50		T6	444
valid_sources[0x5e]	29929	1			T4	1		T5	39		T6	473
valid_sources[0x5f]	32877	1			T4	2		T5	49		T6	403
valid_sources[0x60]	31193	1			T4	11		T5	54		T6	419
valid_sources[0x61]	32681	1			T4	4		T5	72		T6	448
valid_sources[0x62]	30024	1			T4	5		T5	17		T6	407
valid_sources[0x63]	28030	1			T4	11		T5	39		T6	416
valid_sources[0x64]	30588	1			T4	16		T5	44		T6	426
valid_sources[0x65]	27882	1			T4	22		T5	35		T6	457
valid_sources[0x66]	29457	1			T4	1		T5	46		T6	415
valid_sources[0x67]	28641	1			T4	21		T5	22		T6	408
valid_sources[0x68]	28619	1			T4	1		T5	43		T6	421
valid_sources[0x69]	30030	1			T4	5		T5	75		T6	448
valid_sources[0x6a]	29644	1			T5	70		T6	405		T7	59
valid_sources[0x6b]	31821	1			T4	13		T5	8		T6	418
valid_sources[0x6c]	30550	1			T4	6		T5	48		T6	431
valid_sources[0x6d]	28970	1			T4	6		T5	39		T6	400
valid_sources[0x6e]	28245	1			T4	3		T5	37		T6	414
valid_sources[0x6f]	31909	1			T4	7		T5	65		T6	441
valid_sources[0x70]	30300	1			T4	14		T5	33		T6	461
valid_sources[0x71]	28521	1			T4	18		T5	28		T6	426
valid_sources[0x72]	29508	1			T4	13		T5	23		T6	372
valid_sources[0x73]	33134	1			T4	9		T5	39		T6	378
valid_sources[0x74]	28843	1			T4	23		T5	11		T6	451
valid_sources[0x75]	31178	1			T4	3		T5	43		T6	461
valid_sources[0x76]	28793	1			T4	5		T5	46		T6	466
valid_sources[0x77]	28099	1			T4	2		T5	69		T6	437
valid_sources[0x78]	28985	1			T4	11		T5	46		T6	425
valid_sources[0x79]	28218	1			T4	6		T5	55		T6	461
valid_sources[0x7a]	29004	1			T4	6		T5	49		T6	491
valid_sources[0x7b]	32437	1			T4	13		T5	105		T6	414
valid_sources[0x7c]	33007	1			T4	1		T5	64		T6	452
valid_sources[0x7d]	28223	1			T4	2		T5	125		T6	417
valid_sources[0x7e]	29312	1			T5	55		T6	377		T7	49
valid_sources[0x7f]	28520	1			T4	9		T5	60		T6	475
valid_sources[0x80]	31948	1			T4	7		T5	78		T6	393

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1098168

1

T1

1

T2

2

T3

42

values[0x0]

all_enables

biggest_size

1571606

1

T1

433

T2

456

T3

16

values[0x1]

all_enables

biggest_size

1548127

1

T1

442

T2

437

T3

6