Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3621046

1

T1

1

T2

6

T3

166

full_word

4216975

1

T1

876

T2

895

T3

64

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7837601	1			T1	877		T2	901		T3	230
auto[TlIntgErrCmd]	149	1			T92	2		T93	10		T98	6
auto[TlIntgErrData]	122	1			T92	12		T93	4		T98	6
auto[TlIntgErrBoth]	149	1			T92	6		T93	6		T98	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4378560

1

T1

2

T2

5

T3

152

auto[1]

3459461

1

T1

875

T2

896

T3

78

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3280116	1			T1	1		T2	3		T3	110
auto[TlIntgErrNone]	partial	auto[1]	340547	1			T2	3		T3	56		T4	10
auto[TlIntgErrNone]	full_word	auto[0]	1098257	1			T1	1		T2	2		T3	42
auto[TlIntgErrNone]	full_word	auto[1]	3118681	1			T1	875		T2	893		T3	22
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T92	2		T93	4		T98	3
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T93	5		T98	2		T113	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T98	1		T143	1		T160	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T93	1		T114	1		T161	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T92	4		T93	2		T98	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T92	8		T93	2		T98	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T98	1		T161	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T113	1		T115	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T93	2		T113	1		T114	3
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T92	4		T93	2		T98	7
auto[TlIntgErrBoth]	full_word	auto[0]	10	1			T92	2		T93	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T93	1		T98	1		T161	1