Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462638574	2806412	0	0
DepthKnown_A	462638574	462504041	0	0
RvalidKnown_A	462638574	462504041	0	0
WreadyKnown_A	462638574	462504041	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	2806412	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	1663	0	0
T5	237306	15803	0	0
T6	529389	19126	0	0
T7	287085	4991	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	1663	0	0
T11	0	832	0	0
T12	0	6653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462638574	2980261	0	0
DepthKnown_A	462638574	462504041	0	0
RvalidKnown_A	462638574	462504041	0	0
WreadyKnown_A	462638574	462504041	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	2980261	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	11648	0	0
T6	529389	10816	0	0
T7	287085	16393	0	0
T8	110786	2608	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	4160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462638574	177463	0	0
DepthKnown_A	462638574	462504041	0	0
RvalidKnown_A	462638574	462504041	0	0
WreadyKnown_A	462638574	462504041	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	177463	0	0
T5	237306	536	0	0
T6	529389	1532	0	0
T7	287085	1004	0	0
T8	110786	0	0	0
T9	36973	0	0	0
T10	2857	0	0	0
T11	576444	0	0	0
T12	138219	842	0	0
T13	960897	348	0	0
T14	0	1521	0	0
T16	0	1793	0	0
T28	0	100	0	0
T31	0	1137	0	0
T32	0	64	0	0
T33	34433	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462638574	386058	0	0
DepthKnown_A	462638574	462504041	0	0
RvalidKnown_A	462638574	462504041	0	0
WreadyKnown_A	462638574	462504041	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	386058	0	0
T5	237306	536	0	0
T6	529389	1532	0	0
T7	287085	4671	0	0
T8	110786	0	0	0
T9	36973	0	0	0
T10	2857	0	0	0
T11	576444	0	0	0
T12	138219	842	0	0
T13	960897	1633	0	0
T14	0	4557	0	0
T16	0	1793	0	0
T28	0	100	0	0
T31	0	1137	0	0
T32	0	169	0	0
T33	34433	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462638574	6212947	0	0
DepthKnown_A	462638574	462504041	0	0
RvalidKnown_A	462638574	462504041	0	0
WreadyKnown_A	462638574	462504041	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	6212947	0	0
T1	7257	45	0	0
T2	18414	69	0	0
T3	6097	230	0	0
T4	25529	1030	0	0
T5	237306	1358	0	0
T6	529389	96972	0	0
T7	287085	8951	0	0
T8	110786	2504	0	0
T9	36973	192	0	0
T10	2857	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462638574	12312157	0	0
DepthKnown_A	462638574	462504041	0	0
RvalidKnown_A	462638574	462504041	0	0
WreadyKnown_A	462638574	462504041	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	12312157	0	0
T1	7257	45	0	0
T2	18414	69	0	0
T3	6097	653	0	0
T4	25529	1029	0	0
T5	237306	1356	0	0
T6	529389	96413	0	0
T7	287085	36119	0	0
T8	110786	7635	0	0
T9	36973	623	0	0
T10	2857	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462638574	462504041	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0