Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T12
1	0	Covered	T6,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Unreachable
1	1	Covered	T6,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	742268665	599997691	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	742268665	3534146	0	0
GntImpliesValid_A	742268665	3534146	0	0
GrantKnown_A	742268665	599997691	0	0
IdxKnown_A	742268665	599997691	0	0
IndexIsCorrect_A	742268665	3534146	0	0
LockArbDecision_A	742268665	0	0	0
NoReadyValidNoGrant_A	742268665	0	0	0
ReadyAndValidImplyGrant_A	742268665	3534146	0	0
ReqAndReadyImplyGrant_A	742268665	3534146	0	0
ReqImpliesValid_A	742268665	3534146	0	0
ReqStaysHighUntilGranted0_M	742268665	0	0	0
RoundRobin_A	742268665	1	0	976
ValidKnown_A	742268665	599997691	0	0
gen_data_port_assertion.DataFlow_A	742268665	3534146	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	599997691	0	0
T1	11417	11329	0	0
T2	38281	37188	0	0
T3	6097	5838	0	0
T4	67181	66827	0	0
T5	776176	773000	0	0
T6	1847979	1183529	0	0
T7	1812407	1041234	0	0
T8	151326	130971	0	0
T9	89067	61867	0	0
T10	2857	2767	0	0
T11	285588	141600	0	0
T12	550932	272858	0	0
T13	191451	189403	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	3534146	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	776176	15013	0	0
T6	1847979	26801	0	0
T7	1812407	11838	0	0
T8	151326	832	0	0
T9	89067	0	0	0
T10	2857	832	0	0
T11	285588	832	0	0
T12	550932	10534	0	0
T13	382902	1845	0	0
T14	109163	11571	0	0
T16	0	15196	0	0
T31	0	6558	0	0
T32	0	3002	0	0
T33	123216	0	0	0
T40	0	4671	0	0
T44	85144	0	0	0
T46	0	2	0	0
T47	0	2948	0	0
T48	0	4360	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	3534146	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	776176	15013	0	0
T6	1847979	26801	0	0
T7	1812407	11838	0	0
T8	151326	832	0	0
T9	89067	0	0	0
T10	2857	832	0	0
T11	285588	832	0	0
T12	550932	10534	0	0
T13	382902	1845	0	0
T14	109163	11571	0	0
T16	0	15196	0	0
T31	0	6558	0	0
T32	0	3002	0	0
T33	123216	0	0	0
T40	0	4671	0	0
T44	85144	0	0	0
T46	0	2	0	0
T47	0	2948	0	0
T48	0	4360	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	599997691	0	0
T1	11417	11329	0	0
T2	38281	37188	0	0
T3	6097	5838	0	0
T4	67181	66827	0	0
T5	776176	773000	0	0
T6	1847979	1183529	0	0
T7	1812407	1041234	0	0
T8	151326	130971	0	0
T9	89067	61867	0	0
T10	2857	2767	0	0
T11	285588	141600	0	0
T12	550932	272858	0	0
T13	191451	189403	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	599997691	0	0
T1	11417	11329	0	0
T2	38281	37188	0	0
T3	6097	5838	0	0
T4	67181	66827	0	0
T5	776176	773000	0	0
T6	1847979	1183529	0	0
T7	1812407	1041234	0	0
T8	151326	130971	0	0
T9	89067	61867	0	0
T10	2857	2767	0	0
T11	285588	141600	0	0
T12	550932	272858	0	0
T13	191451	189403	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	3534146	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	776176	15013	0	0
T6	1847979	26801	0	0
T7	1812407	11838	0	0
T8	151326	832	0	0
T9	89067	0	0	0
T10	2857	832	0	0
T11	285588	832	0	0
T12	550932	10534	0	0
T13	382902	1845	0	0
T14	109163	11571	0	0
T16	0	15196	0	0
T31	0	6558	0	0
T32	0	3002	0	0
T33	123216	0	0	0
T40	0	4671	0	0
T44	85144	0	0	0
T46	0	2	0	0
T47	0	2948	0	0
T48	0	4360	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	3534146	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	776176	15013	0	0
T6	1847979	26801	0	0
T7	1812407	11838	0	0
T8	151326	832	0	0
T9	89067	0	0	0
T10	2857	832	0	0
T11	285588	832	0	0
T12	550932	10534	0	0
T13	382902	1845	0	0
T14	109163	11571	0	0
T16	0	15196	0	0
T31	0	6558	0	0
T32	0	3002	0	0
T33	123216	0	0	0
T40	0	4671	0	0
T44	85144	0	0	0
T46	0	2	0	0
T47	0	2948	0	0
T48	0	4360	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	3534146	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	776176	15013	0	0
T6	1847979	26801	0	0
T7	1812407	11838	0	0
T8	151326	832	0	0
T9	89067	0	0	0
T10	2857	832	0	0
T11	285588	832	0	0
T12	550932	10534	0	0
T13	382902	1845	0	0
T14	109163	11571	0	0
T16	0	15196	0	0
T31	0	6558	0	0
T32	0	3002	0	0
T33	123216	0	0	0
T40	0	4671	0	0
T44	85144	0	0	0
T46	0	2	0	0
T47	0	2948	0	0
T48	0	4360	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	3534146	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	776176	15013	0	0
T6	1847979	26801	0	0
T7	1812407	11838	0	0
T8	151326	832	0	0
T9	89067	0	0	0
T10	2857	832	0	0
T11	285588	832	0	0
T12	550932	10534	0	0
T13	382902	1845	0	0
T14	109163	11571	0	0
T16	0	15196	0	0
T31	0	6558	0	0
T32	0	3002	0	0
T33	123216	0	0	0
T40	0	4671	0	0
T44	85144	0	0	0
T46	0	2	0	0
T47	0	2948	0	0
T48	0	4360	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	1	0	976
T49	690392	1	0	1
T50	14855	0	0	1
T51	104554	0	0	1
T52	566399	0	0	1
T53	86865	0	0	1
T54	554276	0	0	1
T55	42888	0	0	1
T56	2676	0	0	1
T57	292980	0	0	1
T58	878203	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	599997691	0	0
T1	11417	11329	0	0
T2	38281	37188	0	0
T3	6097	5838	0	0
T4	67181	66827	0	0
T5	776176	773000	0	0
T6	1847979	1183529	0	0
T7	1812407	1041234	0	0
T8	151326	130971	0	0
T9	89067	61867	0	0
T10	2857	2767	0	0
T11	285588	141600	0	0
T12	550932	272858	0	0
T13	191451	189403	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742268665	3534146	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	776176	15013	0	0
T6	1847979	26801	0	0
T7	1812407	11838	0	0
T8	151326	832	0	0
T9	89067	0	0	0
T10	2857	832	0	0
T11	285588	832	0	0
T12	550932	10534	0	0
T13	382902	1845	0	0
T14	109163	11571	0	0
T16	0	15196	0	0
T31	0	6558	0	0
T32	0	3002	0	0
T33	123216	0	0	0
T40	0	4671	0	0
T44	85144	0	0	0
T46	0	2	0	0
T47	0	2948	0	0
T48	0	4360	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T12
1	0	Covered	T6,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Unreachable
1	1	Covered	T6,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T12
0	0	1	Unreachable
0	0	0	Covered	T6,T7,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	140909002	24901154	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	140909002	564768	0	0
GntImpliesValid_A	140909002	564768	0	0
GrantKnown_A	140909002	24901154	0	0
IdxKnown_A	140909002	24901154	0	0
IndexIsCorrect_A	140909002	564768	0	0
LockArbDecision_A	140909002	0	0	0
NoReadyValidNoGrant_A	140909002	0	0	0
ReadyAndValidImplyGrant_A	140909002	564768	0	0
ReqAndReadyImplyGrant_A	140909002	564768	0	0
ReqImpliesValid_A	140909002	564768	0	0
ReqStaysHighUntilGranted0_M	140909002	0	0	0
RoundRobin_A	140909002	0	0	0
ValidKnown_A	140909002	24901154	0	0
gen_data_port_assertion.DataFlow_A	140909002	564768	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	24901154	0	0
T6	659295	122208	0	0
T7	762661	389424	0	0
T8	20270	0	0	0
T9	26047	24944	0	0
T11	142794	0	0	0
T12	275466	69240	0	0
T13	191451	20280	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	564768	0	0
T6	659295	5305	0	0
T7	762661	4894	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	3121	0	0
T13	191451	1072	0	0
T14	109163	4745	0	0
T16	0	5877	0	0
T31	0	5423	0	0
T33	61608	0	0	0
T40	0	4671	0	0
T44	42572	0	0	0
T47	0	2948	0	0
T48	0	4360	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	564768	0	0
T6	659295	5305	0	0
T7	762661	4894	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	3121	0	0
T13	191451	1072	0	0
T14	109163	4745	0	0
T16	0	5877	0	0
T31	0	5423	0	0
T33	61608	0	0	0
T40	0	4671	0	0
T44	42572	0	0	0
T47	0	2948	0	0
T48	0	4360	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	24901154	0	0
T6	659295	122208	0	0
T7	762661	389424	0	0
T8	20270	0	0	0
T9	26047	24944	0	0
T11	142794	0	0	0
T12	275466	69240	0	0
T13	191451	20280	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	24901154	0	0
T6	659295	122208	0	0
T7	762661	389424	0	0
T8	20270	0	0	0
T9	26047	24944	0	0
T11	142794	0	0	0
T12	275466	69240	0	0
T13	191451	20280	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	564768	0	0
T6	659295	5305	0	0
T7	762661	4894	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	3121	0	0
T13	191451	1072	0	0
T14	109163	4745	0	0
T16	0	5877	0	0
T31	0	5423	0	0
T33	61608	0	0	0
T40	0	4671	0	0
T44	42572	0	0	0
T47	0	2948	0	0
T48	0	4360	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	564768	0	0
T6	659295	5305	0	0
T7	762661	4894	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	3121	0	0
T13	191451	1072	0	0
T14	109163	4745	0	0
T16	0	5877	0	0
T31	0	5423	0	0
T33	61608	0	0	0
T40	0	4671	0	0
T44	42572	0	0	0
T47	0	2948	0	0
T48	0	4360	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	564768	0	0
T6	659295	5305	0	0
T7	762661	4894	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	3121	0	0
T13	191451	1072	0	0
T14	109163	4745	0	0
T16	0	5877	0	0
T31	0	5423	0	0
T33	61608	0	0	0
T40	0	4671	0	0
T44	42572	0	0	0
T47	0	2948	0	0
T48	0	4360	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	564768	0	0
T6	659295	5305	0	0
T7	762661	4894	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	3121	0	0
T13	191451	1072	0	0
T14	109163	4745	0	0
T16	0	5877	0	0
T31	0	5423	0	0
T33	61608	0	0	0
T40	0	4671	0	0
T44	42572	0	0	0
T47	0	2948	0	0
T48	0	4360	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	24901154	0	0
T6	659295	122208	0	0
T7	762661	389424	0	0
T8	20270	0	0	0
T9	26047	24944	0	0
T11	142794	0	0	0
T12	275466	69240	0	0
T13	191451	20280	0	0
T14	109163	177432	0	0
T15	0	144	0	0
T16	0	142624	0	0
T23	0	504	0	0
T24	0	216	0	0
T33	61608	0	0	0
T44	42572	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	564768	0	0
T6	659295	5305	0	0
T7	762661	4894	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	3121	0	0
T13	191451	1072	0	0
T14	109163	4745	0	0
T16	0	5877	0	0
T31	0	5423	0	0
T33	61608	0	0	0
T40	0	4671	0	0
T44	42572	0	0	0
T47	0	2948	0	0
T48	0	4360	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	140909002	114733972	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	140909002	781201	0	0
GntImpliesValid_A	140909002	781201	0	0
GrantKnown_A	140909002	114733972	0	0
IdxKnown_A	140909002	114733972	0	0
IndexIsCorrect_A	140909002	781201	0	0
LockArbDecision_A	140909002	0	0	0
NoReadyValidNoGrant_A	140909002	0	0	0
ReadyAndValidImplyGrant_A	140909002	781201	0	0
ReqAndReadyImplyGrant_A	140909002	781201	0	0
ReqImpliesValid_A	140909002	781201	0	0
ReqStaysHighUntilGranted0_M	140909002	0	0	0
RoundRobin_A	140909002	0	0	0
ValidKnown_A	140909002	114733972	0	0
gen_data_port_assertion.DataFlow_A	140909002	781201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	114733972	0	0
T1	4160	4160	0	0
T2	19867	18850	0	0
T4	41652	41376	0	0
T5	538870	535793	0	0
T6	659295	531938	0	0
T7	762661	365106	0	0
T8	20270	20270	0	0
T9	26047	0	0	0
T11	142794	141600	0	0
T12	275466	203618	0	0
T13	0	169123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	781201	0	0
T5	538870	2793	0	0
T6	659295	7200	0	0
T7	762661	412	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	1446	0	0
T13	191451	773	0	0
T14	0	6826	0	0
T16	0	9319	0	0
T31	0	1135	0	0
T32	0	3002	0	0
T33	61608	0	0	0
T44	42572	0	0	0
T46	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	781201	0	0
T5	538870	2793	0	0
T6	659295	7200	0	0
T7	762661	412	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	1446	0	0
T13	191451	773	0	0
T14	0	6826	0	0
T16	0	9319	0	0
T31	0	1135	0	0
T32	0	3002	0	0
T33	61608	0	0	0
T44	42572	0	0	0
T46	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	114733972	0	0
T1	4160	4160	0	0
T2	19867	18850	0	0
T4	41652	41376	0	0
T5	538870	535793	0	0
T6	659295	531938	0	0
T7	762661	365106	0	0
T8	20270	20270	0	0
T9	26047	0	0	0
T11	142794	141600	0	0
T12	275466	203618	0	0
T13	0	169123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	114733972	0	0
T1	4160	4160	0	0
T2	19867	18850	0	0
T4	41652	41376	0	0
T5	538870	535793	0	0
T6	659295	531938	0	0
T7	762661	365106	0	0
T8	20270	20270	0	0
T9	26047	0	0	0
T11	142794	141600	0	0
T12	275466	203618	0	0
T13	0	169123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	781201	0	0
T5	538870	2793	0	0
T6	659295	7200	0	0
T7	762661	412	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	1446	0	0
T13	191451	773	0	0
T14	0	6826	0	0
T16	0	9319	0	0
T31	0	1135	0	0
T32	0	3002	0	0
T33	61608	0	0	0
T44	42572	0	0	0
T46	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	781201	0	0
T5	538870	2793	0	0
T6	659295	7200	0	0
T7	762661	412	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	1446	0	0
T13	191451	773	0	0
T14	0	6826	0	0
T16	0	9319	0	0
T31	0	1135	0	0
T32	0	3002	0	0
T33	61608	0	0	0
T44	42572	0	0	0
T46	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	781201	0	0
T5	538870	2793	0	0
T6	659295	7200	0	0
T7	762661	412	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	1446	0	0
T13	191451	773	0	0
T14	0	6826	0	0
T16	0	9319	0	0
T31	0	1135	0	0
T32	0	3002	0	0
T33	61608	0	0	0
T44	42572	0	0	0
T46	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	781201	0	0
T5	538870	2793	0	0
T6	659295	7200	0	0
T7	762661	412	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	1446	0	0
T13	191451	773	0	0
T14	0	6826	0	0
T16	0	9319	0	0
T31	0	1135	0	0
T32	0	3002	0	0
T33	61608	0	0	0
T44	42572	0	0	0
T46	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	114733972	0	0
T1	4160	4160	0	0
T2	19867	18850	0	0
T4	41652	41376	0	0
T5	538870	535793	0	0
T6	659295	531938	0	0
T7	762661	365106	0	0
T8	20270	20270	0	0
T9	26047	0	0	0
T11	142794	141600	0	0
T12	275466	203618	0	0
T13	0	169123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140909002	781201	0	0
T5	538870	2793	0	0
T6	659295	7200	0	0
T7	762661	412	0	0
T8	20270	0	0	0
T9	26047	0	0	0
T11	142794	0	0	0
T12	275466	1446	0	0
T13	191451	773	0	0
T14	0	6826	0	0
T16	0	9319	0	0
T31	0	1135	0	0
T32	0	3002	0	0
T33	61608	0	0	0
T44	42572	0	0	0
T46	0	2	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	460450661	460362565	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	460450661	2188177	0	0
GntImpliesValid_A	460450661	2188177	0	0
GrantKnown_A	460450661	460362565	0	0
IdxKnown_A	460450661	460362565	0	0
IndexIsCorrect_A	460450661	2188177	0	0
LockArbDecision_A	460450661	0	0	0
NoReadyValidNoGrant_A	460450661	0	0	0
ReadyAndValidImplyGrant_A	460450661	2188177	0	0
ReqAndReadyImplyGrant_A	460450661	2188177	0	0
ReqImpliesValid_A	460450661	2188177	0	0
ReqStaysHighUntilGranted0_M	460450661	0	0	0
RoundRobin_A	460450661	1	0	976
ValidKnown_A	460450661	460362565	0	0
gen_data_port_assertion.DataFlow_A	460450661	2188177	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	460362565	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	2188177	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	12220	0	0
T6	529389	14296	0	0
T7	287085	6532	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	5967	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	2188177	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	12220	0	0
T6	529389	14296	0	0
T7	287085	6532	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	5967	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	460362565	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	460362565	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	2188177	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	12220	0	0
T6	529389	14296	0	0
T7	287085	6532	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	5967	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	2188177	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	12220	0	0
T6	529389	14296	0	0
T7	287085	6532	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	5967	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	2188177	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	12220	0	0
T6	529389	14296	0	0
T7	287085	6532	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	5967	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	2188177	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	12220	0	0
T6	529389	14296	0	0
T7	287085	6532	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	5967	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	1	0	976
T49	690392	1	0	1
T50	14855	0	0	1
T51	104554	0	0	1
T52	566399	0	0	1
T53	86865	0	0	1
T54	554276	0	0	1
T55	42888	0	0	1
T56	2676	0	0	1
T57	292980	0	0	1
T58	878203	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	460362565	0	0
T1	7257	7169	0	0
T2	18414	18338	0	0
T3	6097	5838	0	0
T4	25529	25451	0	0
T5	237306	237207	0	0
T6	529389	529383	0	0
T7	287085	286704	0	0
T8	110786	110701	0	0
T9	36973	36923	0	0
T10	2857	2767	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460450661	2188177	0	0
T1	7257	832	0	0
T2	18414	832	0	0
T3	6097	0	0	0
T4	25529	832	0	0
T5	237306	12220	0	0
T6	529389	14296	0	0
T7	287085	6532	0	0
T8	110786	832	0	0
T9	36973	0	0	0
T10	2857	832	0	0
T11	0	832	0	0
T12	0	5967	0	0