Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3899 |
0 |
0 |
T92 |
53914 |
3 |
0 |
0 |
T93 |
60767 |
3 |
0 |
0 |
T94 |
6467 |
17 |
0 |
0 |
T95 |
2867 |
10 |
0 |
0 |
T96 |
4009 |
92 |
0 |
0 |
T97 |
6791 |
304 |
0 |
0 |
T98 |
54393 |
1 |
0 |
0 |
T112 |
5068 |
17 |
0 |
0 |
T113 |
27801 |
3 |
0 |
0 |
T114 |
29328 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1302 |
0 |
0 |
T93 |
60767 |
45 |
0 |
0 |
T115 |
67653 |
66 |
0 |
0 |
T116 |
15552 |
16 |
0 |
0 |
T123 |
113620 |
766 |
0 |
0 |
T124 |
6963 |
9 |
0 |
0 |
T136 |
20412 |
32 |
0 |
0 |
T142 |
20746 |
40 |
0 |
0 |
T143 |
64110 |
34 |
0 |
0 |
T144 |
103312 |
114 |
0 |
0 |
T145 |
5586 |
9 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1386 |
0 |
0 |
T93 |
60767 |
46 |
0 |
0 |
T115 |
67653 |
88 |
0 |
0 |
T116 |
15552 |
23 |
0 |
0 |
T123 |
113620 |
771 |
0 |
0 |
T124 |
6963 |
9 |
0 |
0 |
T136 |
20412 |
29 |
0 |
0 |
T142 |
20746 |
62 |
0 |
0 |
T143 |
64110 |
52 |
0 |
0 |
T144 |
103312 |
119 |
0 |
0 |
T145 |
5586 |
3 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1887 |
0 |
0 |
T93 |
60767 |
66 |
0 |
0 |
T115 |
67653 |
144 |
0 |
0 |
T116 |
15552 |
32 |
0 |
0 |
T123 |
113620 |
828 |
0 |
0 |
T124 |
6963 |
12 |
0 |
0 |
T136 |
20412 |
71 |
0 |
0 |
T142 |
20746 |
71 |
0 |
0 |
T143 |
64110 |
87 |
0 |
0 |
T144 |
103312 |
204 |
0 |
0 |
T145 |
5586 |
14 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
8078 |
0 |
0 |
T93 |
60767 |
461 |
0 |
0 |
T115 |
67653 |
1194 |
0 |
0 |
T116 |
15552 |
236 |
0 |
0 |
T123 |
113620 |
710 |
0 |
0 |
T124 |
6963 |
5 |
0 |
0 |
T136 |
20412 |
31 |
0 |
0 |
T142 |
20746 |
78 |
0 |
0 |
T143 |
64110 |
572 |
0 |
0 |
T144 |
103312 |
1816 |
0 |
0 |
T145 |
5586 |
92 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
8879 |
0 |
0 |
T93 |
60767 |
591 |
0 |
0 |
T115 |
67653 |
1621 |
0 |
0 |
T116 |
15552 |
239 |
0 |
0 |
T123 |
113620 |
754 |
0 |
0 |
T124 |
6963 |
114 |
0 |
0 |
T136 |
20412 |
63 |
0 |
0 |
T142 |
20746 |
66 |
0 |
0 |
T143 |
64110 |
526 |
0 |
0 |
T144 |
103312 |
2092 |
0 |
0 |
T145 |
5586 |
5 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
7814 |
0 |
0 |
T93 |
60767 |
551 |
0 |
0 |
T115 |
67653 |
1380 |
0 |
0 |
T116 |
15552 |
227 |
0 |
0 |
T123 |
113620 |
814 |
0 |
0 |
T124 |
6963 |
9 |
0 |
0 |
T136 |
20412 |
74 |
0 |
0 |
T142 |
20746 |
48 |
0 |
0 |
T143 |
64110 |
532 |
0 |
0 |
T144 |
103312 |
1566 |
0 |
0 |
T145 |
5586 |
2 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
9019 |
0 |
0 |
T93 |
60767 |
650 |
0 |
0 |
T115 |
67653 |
1427 |
0 |
0 |
T116 |
15552 |
224 |
0 |
0 |
T123 |
113620 |
775 |
0 |
0 |
T124 |
6963 |
239 |
0 |
0 |
T136 |
20412 |
78 |
0 |
0 |
T142 |
20746 |
73 |
0 |
0 |
T143 |
64110 |
845 |
0 |
0 |
T144 |
103312 |
2099 |
0 |
0 |
T145 |
5586 |
80 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
7878 |
0 |
0 |
T93 |
60767 |
742 |
0 |
0 |
T115 |
67653 |
1219 |
0 |
0 |
T116 |
15552 |
253 |
0 |
0 |
T123 |
113620 |
785 |
0 |
0 |
T124 |
6963 |
137 |
0 |
0 |
T136 |
20412 |
67 |
0 |
0 |
T142 |
20746 |
51 |
0 |
0 |
T143 |
64110 |
721 |
0 |
0 |
T144 |
103312 |
1521 |
0 |
0 |
T145 |
5586 |
50 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
8369 |
0 |
0 |
T93 |
60767 |
872 |
0 |
0 |
T115 |
67653 |
1436 |
0 |
0 |
T116 |
15552 |
236 |
0 |
0 |
T123 |
113620 |
730 |
0 |
0 |
T124 |
6963 |
83 |
0 |
0 |
T136 |
20412 |
28 |
0 |
0 |
T142 |
20746 |
81 |
0 |
0 |
T143 |
64110 |
950 |
0 |
0 |
T144 |
103312 |
1470 |
0 |
0 |
T145 |
5586 |
60 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
8006 |
0 |
0 |
T93 |
60767 |
516 |
0 |
0 |
T115 |
67653 |
1101 |
0 |
0 |
T116 |
15552 |
337 |
0 |
0 |
T123 |
113620 |
814 |
0 |
0 |
T124 |
6963 |
123 |
0 |
0 |
T136 |
20412 |
63 |
0 |
0 |
T142 |
20746 |
58 |
0 |
0 |
T143 |
64110 |
909 |
0 |
0 |
T144 |
103312 |
1366 |
0 |
0 |
T145 |
5586 |
6 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
7569 |
0 |
0 |
T93 |
60767 |
524 |
0 |
0 |
T115 |
67653 |
1456 |
0 |
0 |
T116 |
15552 |
30 |
0 |
0 |
T123 |
113620 |
716 |
0 |
0 |
T124 |
6963 |
146 |
0 |
0 |
T136 |
20412 |
101 |
0 |
0 |
T142 |
20746 |
33 |
0 |
0 |
T143 |
64110 |
488 |
0 |
0 |
T144 |
103312 |
1439 |
0 |
0 |
T145 |
5586 |
85 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4275 |
0 |
0 |
T93 |
60767 |
281 |
0 |
0 |
T115 |
67653 |
534 |
0 |
0 |
T116 |
15552 |
99 |
0 |
0 |
T123 |
113620 |
831 |
0 |
0 |
T124 |
6963 |
48 |
0 |
0 |
T136 |
20412 |
78 |
0 |
0 |
T142 |
20746 |
75 |
0 |
0 |
T143 |
64110 |
214 |
0 |
0 |
T144 |
103312 |
831 |
0 |
0 |
T145 |
5586 |
12 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4179 |
0 |
0 |
T93 |
60767 |
368 |
0 |
0 |
T115 |
67653 |
556 |
0 |
0 |
T116 |
15552 |
115 |
0 |
0 |
T123 |
113620 |
819 |
0 |
0 |
T124 |
6963 |
100 |
0 |
0 |
T136 |
20412 |
54 |
0 |
0 |
T142 |
20746 |
110 |
0 |
0 |
T143 |
64110 |
325 |
0 |
0 |
T144 |
103312 |
716 |
0 |
0 |
T145 |
5586 |
29 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4093 |
0 |
0 |
T93 |
60767 |
139 |
0 |
0 |
T115 |
67653 |
483 |
0 |
0 |
T116 |
15552 |
73 |
0 |
0 |
T123 |
113620 |
810 |
0 |
0 |
T124 |
6963 |
7 |
0 |
0 |
T136 |
20412 |
37 |
0 |
0 |
T142 |
20746 |
89 |
0 |
0 |
T143 |
64110 |
346 |
0 |
0 |
T144 |
103312 |
902 |
0 |
0 |
T145 |
5586 |
21 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3969 |
0 |
0 |
T93 |
60767 |
261 |
0 |
0 |
T115 |
67653 |
521 |
0 |
0 |
T116 |
15552 |
113 |
0 |
0 |
T123 |
113620 |
766 |
0 |
0 |
T124 |
6963 |
2 |
0 |
0 |
T136 |
20412 |
86 |
0 |
0 |
T142 |
20746 |
56 |
0 |
0 |
T143 |
64110 |
286 |
0 |
0 |
T144 |
103312 |
664 |
0 |
0 |
T145 |
5586 |
2 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3731 |
0 |
0 |
T93 |
60767 |
261 |
0 |
0 |
T115 |
67653 |
521 |
0 |
0 |
T116 |
15552 |
32 |
0 |
0 |
T123 |
113620 |
792 |
0 |
0 |
T124 |
6963 |
45 |
0 |
0 |
T136 |
20412 |
13 |
0 |
0 |
T142 |
20746 |
64 |
0 |
0 |
T143 |
64110 |
240 |
0 |
0 |
T144 |
103312 |
638 |
0 |
0 |
T145 |
5586 |
6 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4417 |
0 |
0 |
T93 |
60767 |
273 |
0 |
0 |
T115 |
67653 |
532 |
0 |
0 |
T116 |
15552 |
88 |
0 |
0 |
T123 |
113620 |
815 |
0 |
0 |
T124 |
6963 |
44 |
0 |
0 |
T136 |
20412 |
82 |
0 |
0 |
T142 |
20746 |
149 |
0 |
0 |
T143 |
64110 |
276 |
0 |
0 |
T144 |
103312 |
770 |
0 |
0 |
T145 |
5586 |
44 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3840 |
0 |
0 |
T93 |
60767 |
367 |
0 |
0 |
T115 |
67653 |
509 |
0 |
0 |
T116 |
15552 |
106 |
0 |
0 |
T123 |
113620 |
703 |
0 |
0 |
T124 |
6963 |
76 |
0 |
0 |
T136 |
20412 |
75 |
0 |
0 |
T142 |
20746 |
21 |
0 |
0 |
T143 |
64110 |
220 |
0 |
0 |
T144 |
103312 |
763 |
0 |
0 |
T145 |
5586 |
10 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4403 |
0 |
0 |
T93 |
60767 |
224 |
0 |
0 |
T115 |
67653 |
517 |
0 |
0 |
T116 |
15552 |
63 |
0 |
0 |
T123 |
113620 |
826 |
0 |
0 |
T124 |
6963 |
8 |
0 |
0 |
T136 |
20412 |
73 |
0 |
0 |
T142 |
20746 |
72 |
0 |
0 |
T143 |
64110 |
250 |
0 |
0 |
T144 |
103312 |
1075 |
0 |
0 |
T145 |
5586 |
9 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3759 |
0 |
0 |
T93 |
60767 |
247 |
0 |
0 |
T115 |
67653 |
481 |
0 |
0 |
T116 |
15552 |
114 |
0 |
0 |
T123 |
113620 |
726 |
0 |
0 |
T124 |
6963 |
10 |
0 |
0 |
T136 |
20412 |
48 |
0 |
0 |
T142 |
20746 |
64 |
0 |
0 |
T143 |
64110 |
198 |
0 |
0 |
T144 |
103312 |
785 |
0 |
0 |
T145 |
5586 |
39 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4416 |
0 |
0 |
T93 |
60767 |
259 |
0 |
0 |
T115 |
67653 |
632 |
0 |
0 |
T116 |
15552 |
98 |
0 |
0 |
T123 |
113620 |
835 |
0 |
0 |
T124 |
6963 |
107 |
0 |
0 |
T136 |
20412 |
78 |
0 |
0 |
T142 |
20746 |
77 |
0 |
0 |
T143 |
64110 |
200 |
0 |
0 |
T144 |
103312 |
700 |
0 |
0 |
T145 |
5586 |
9 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4276 |
0 |
0 |
T93 |
60767 |
435 |
0 |
0 |
T115 |
67653 |
621 |
0 |
0 |
T116 |
15552 |
93 |
0 |
0 |
T123 |
113620 |
753 |
0 |
0 |
T124 |
6963 |
64 |
0 |
0 |
T136 |
20412 |
110 |
0 |
0 |
T142 |
20746 |
64 |
0 |
0 |
T143 |
64110 |
229 |
0 |
0 |
T144 |
103312 |
958 |
0 |
0 |
T145 |
5586 |
42 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4266 |
0 |
0 |
T93 |
60767 |
331 |
0 |
0 |
T115 |
67653 |
359 |
0 |
0 |
T116 |
15552 |
143 |
0 |
0 |
T123 |
113620 |
833 |
0 |
0 |
T124 |
6963 |
82 |
0 |
0 |
T136 |
20412 |
101 |
0 |
0 |
T142 |
20746 |
45 |
0 |
0 |
T143 |
64110 |
400 |
0 |
0 |
T144 |
103312 |
732 |
0 |
0 |
T145 |
5586 |
1 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4104 |
0 |
0 |
T93 |
60767 |
210 |
0 |
0 |
T115 |
67653 |
697 |
0 |
0 |
T116 |
15552 |
21 |
0 |
0 |
T123 |
113620 |
847 |
0 |
0 |
T124 |
6963 |
56 |
0 |
0 |
T136 |
20412 |
69 |
0 |
0 |
T142 |
20746 |
35 |
0 |
0 |
T143 |
64110 |
290 |
0 |
0 |
T144 |
103312 |
738 |
0 |
0 |
T145 |
5586 |
6 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3972 |
0 |
0 |
T93 |
60767 |
332 |
0 |
0 |
T115 |
67653 |
464 |
0 |
0 |
T116 |
15552 |
43 |
0 |
0 |
T123 |
113620 |
803 |
0 |
0 |
T124 |
6963 |
5 |
0 |
0 |
T136 |
20412 |
71 |
0 |
0 |
T142 |
20746 |
60 |
0 |
0 |
T143 |
64110 |
240 |
0 |
0 |
T144 |
103312 |
853 |
0 |
0 |
T145 |
5586 |
39 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4180 |
0 |
0 |
T93 |
60767 |
276 |
0 |
0 |
T115 |
67653 |
588 |
0 |
0 |
T116 |
15552 |
62 |
0 |
0 |
T123 |
113620 |
845 |
0 |
0 |
T124 |
6963 |
51 |
0 |
0 |
T136 |
20412 |
54 |
0 |
0 |
T142 |
20746 |
86 |
0 |
0 |
T143 |
64110 |
191 |
0 |
0 |
T144 |
103312 |
816 |
0 |
0 |
T145 |
5586 |
27 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3802 |
0 |
0 |
T93 |
60767 |
254 |
0 |
0 |
T115 |
67653 |
508 |
0 |
0 |
T116 |
15552 |
99 |
0 |
0 |
T123 |
113620 |
781 |
0 |
0 |
T124 |
6963 |
6 |
0 |
0 |
T136 |
20412 |
38 |
0 |
0 |
T142 |
20746 |
54 |
0 |
0 |
T143 |
64110 |
233 |
0 |
0 |
T144 |
103312 |
707 |
0 |
0 |
T146 |
9541 |
40 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3731 |
0 |
0 |
T93 |
60767 |
296 |
0 |
0 |
T115 |
67653 |
356 |
0 |
0 |
T116 |
15552 |
48 |
0 |
0 |
T123 |
113620 |
784 |
0 |
0 |
T124 |
6963 |
43 |
0 |
0 |
T136 |
20412 |
22 |
0 |
0 |
T142 |
20746 |
66 |
0 |
0 |
T143 |
64110 |
334 |
0 |
0 |
T144 |
103312 |
721 |
0 |
0 |
T146 |
9541 |
24 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3788 |
0 |
0 |
T93 |
60767 |
196 |
0 |
0 |
T115 |
67653 |
572 |
0 |
0 |
T116 |
15552 |
116 |
0 |
0 |
T123 |
113620 |
837 |
0 |
0 |
T124 |
6963 |
53 |
0 |
0 |
T136 |
20412 |
60 |
0 |
0 |
T142 |
20746 |
146 |
0 |
0 |
T143 |
64110 |
189 |
0 |
0 |
T144 |
103312 |
670 |
0 |
0 |
T146 |
9541 |
44 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3982 |
0 |
0 |
T93 |
60767 |
284 |
0 |
0 |
T115 |
67653 |
325 |
0 |
0 |
T116 |
15552 |
14 |
0 |
0 |
T123 |
113620 |
814 |
0 |
0 |
T124 |
6963 |
76 |
0 |
0 |
T136 |
20412 |
49 |
0 |
0 |
T142 |
20746 |
75 |
0 |
0 |
T143 |
64110 |
270 |
0 |
0 |
T144 |
103312 |
790 |
0 |
0 |
T145 |
5586 |
21 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4535 |
0 |
0 |
T93 |
60767 |
193 |
0 |
0 |
T115 |
67653 |
768 |
0 |
0 |
T116 |
15552 |
96 |
0 |
0 |
T123 |
113620 |
802 |
0 |
0 |
T124 |
6963 |
41 |
0 |
0 |
T136 |
20412 |
65 |
0 |
0 |
T142 |
20746 |
42 |
0 |
0 |
T143 |
64110 |
289 |
0 |
0 |
T144 |
103312 |
854 |
0 |
0 |
T146 |
9541 |
4 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4233 |
0 |
0 |
T93 |
60767 |
346 |
0 |
0 |
T115 |
67653 |
515 |
0 |
0 |
T116 |
15552 |
113 |
0 |
0 |
T123 |
113620 |
794 |
0 |
0 |
T124 |
6963 |
95 |
0 |
0 |
T136 |
20412 |
62 |
0 |
0 |
T142 |
20746 |
47 |
0 |
0 |
T143 |
64110 |
205 |
0 |
0 |
T144 |
103312 |
819 |
0 |
0 |
T145 |
5586 |
26 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3967 |
0 |
0 |
T93 |
60767 |
382 |
0 |
0 |
T115 |
67653 |
472 |
0 |
0 |
T116 |
15552 |
81 |
0 |
0 |
T123 |
113620 |
760 |
0 |
0 |
T124 |
6963 |
5 |
0 |
0 |
T136 |
20412 |
60 |
0 |
0 |
T142 |
20746 |
64 |
0 |
0 |
T143 |
64110 |
351 |
0 |
0 |
T144 |
103312 |
776 |
0 |
0 |
T145 |
5586 |
7 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3783 |
0 |
0 |
T93 |
60767 |
203 |
0 |
0 |
T115 |
67653 |
353 |
0 |
0 |
T116 |
15552 |
119 |
0 |
0 |
T123 |
113620 |
887 |
0 |
0 |
T124 |
6963 |
40 |
0 |
0 |
T136 |
20412 |
24 |
0 |
0 |
T142 |
20746 |
39 |
0 |
0 |
T143 |
64110 |
360 |
0 |
0 |
T144 |
103312 |
542 |
0 |
0 |
T145 |
5586 |
46 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
4116 |
0 |
0 |
T93 |
60767 |
300 |
0 |
0 |
T115 |
67653 |
476 |
0 |
0 |
T116 |
15552 |
70 |
0 |
0 |
T123 |
113620 |
794 |
0 |
0 |
T124 |
6963 |
56 |
0 |
0 |
T136 |
20412 |
30 |
0 |
0 |
T142 |
20746 |
36 |
0 |
0 |
T143 |
64110 |
356 |
0 |
0 |
T144 |
103312 |
847 |
0 |
0 |
T145 |
5586 |
2 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1551 |
0 |
0 |
T93 |
60767 |
58 |
0 |
0 |
T115 |
67653 |
90 |
0 |
0 |
T116 |
15552 |
20 |
0 |
0 |
T123 |
113620 |
787 |
0 |
0 |
T124 |
6963 |
3 |
0 |
0 |
T136 |
20412 |
63 |
0 |
0 |
T142 |
20746 |
69 |
0 |
0 |
T143 |
64110 |
94 |
0 |
0 |
T144 |
103312 |
136 |
0 |
0 |
T145 |
5586 |
1 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1853 |
0 |
0 |
T93 |
60767 |
69 |
0 |
0 |
T115 |
67653 |
139 |
0 |
0 |
T116 |
15552 |
12 |
0 |
0 |
T123 |
113620 |
910 |
0 |
0 |
T124 |
6963 |
9 |
0 |
0 |
T136 |
20412 |
41 |
0 |
0 |
T142 |
20746 |
118 |
0 |
0 |
T143 |
64110 |
74 |
0 |
0 |
T144 |
103312 |
160 |
0 |
0 |
T145 |
5586 |
1 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1646 |
0 |
0 |
T93 |
60767 |
69 |
0 |
0 |
T115 |
67653 |
113 |
0 |
0 |
T116 |
15552 |
30 |
0 |
0 |
T123 |
113620 |
727 |
0 |
0 |
T124 |
6963 |
12 |
0 |
0 |
T136 |
20412 |
108 |
0 |
0 |
T142 |
20746 |
70 |
0 |
0 |
T143 |
64110 |
99 |
0 |
0 |
T144 |
103312 |
157 |
0 |
0 |
T145 |
5586 |
3 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1662 |
0 |
0 |
T93 |
60767 |
32 |
0 |
0 |
T115 |
67653 |
144 |
0 |
0 |
T116 |
15552 |
25 |
0 |
0 |
T123 |
113620 |
853 |
0 |
0 |
T124 |
6963 |
3 |
0 |
0 |
T136 |
20412 |
30 |
0 |
0 |
T142 |
20746 |
94 |
0 |
0 |
T143 |
64110 |
57 |
0 |
0 |
T144 |
103312 |
151 |
0 |
0 |
T145 |
5586 |
6 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
2015 |
0 |
0 |
T93 |
60767 |
75 |
0 |
0 |
T115 |
67653 |
153 |
0 |
0 |
T116 |
15552 |
41 |
0 |
0 |
T123 |
113620 |
775 |
0 |
0 |
T124 |
6963 |
2 |
0 |
0 |
T136 |
20412 |
85 |
0 |
0 |
T142 |
20746 |
97 |
0 |
0 |
T143 |
64110 |
117 |
0 |
0 |
T144 |
103312 |
241 |
0 |
0 |
T145 |
5586 |
3 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
3668 |
0 |
0 |
T3 |
6097 |
54 |
0 |
0 |
T4 |
25529 |
0 |
0 |
0 |
T5 |
237306 |
0 |
0 |
0 |
T6 |
529389 |
0 |
0 |
0 |
T7 |
287085 |
50 |
0 |
0 |
T8 |
110786 |
0 |
0 |
0 |
T9 |
36973 |
0 |
0 |
0 |
T10 |
2857 |
0 |
0 |
0 |
T11 |
576444 |
0 |
0 |
0 |
T12 |
138219 |
0 |
0 |
0 |
T13 |
0 |
41 |
0 |
0 |
T17 |
0 |
61 |
0 |
0 |
T18 |
0 |
24 |
0 |
0 |
T147 |
0 |
35 |
0 |
0 |
T148 |
0 |
10 |
0 |
0 |
T149 |
0 |
61 |
0 |
0 |
T150 |
0 |
32 |
0 |
0 |
T151 |
0 |
24 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1677 |
0 |
0 |
T93 |
60767 |
26 |
0 |
0 |
T115 |
67653 |
117 |
0 |
0 |
T116 |
15552 |
16 |
0 |
0 |
T123 |
113620 |
867 |
0 |
0 |
T124 |
6963 |
19 |
0 |
0 |
T136 |
20412 |
101 |
0 |
0 |
T142 |
20746 |
44 |
0 |
0 |
T143 |
64110 |
83 |
0 |
0 |
T144 |
103312 |
196 |
0 |
0 |
T146 |
9541 |
8 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1732 |
0 |
0 |
T93 |
60767 |
56 |
0 |
0 |
T115 |
67653 |
141 |
0 |
0 |
T116 |
15552 |
43 |
0 |
0 |
T123 |
113620 |
858 |
0 |
0 |
T124 |
6963 |
11 |
0 |
0 |
T136 |
20412 |
49 |
0 |
0 |
T142 |
20746 |
80 |
0 |
0 |
T143 |
64110 |
52 |
0 |
0 |
T144 |
103312 |
159 |
0 |
0 |
T145 |
5586 |
2 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1393 |
0 |
0 |
T93 |
60767 |
36 |
0 |
0 |
T115 |
67653 |
81 |
0 |
0 |
T116 |
15552 |
21 |
0 |
0 |
T123 |
113620 |
731 |
0 |
0 |
T124 |
6963 |
6 |
0 |
0 |
T136 |
20412 |
81 |
0 |
0 |
T142 |
20746 |
61 |
0 |
0 |
T143 |
64110 |
58 |
0 |
0 |
T144 |
103312 |
115 |
0 |
0 |
T145 |
5586 |
3 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1465 |
0 |
0 |
T93 |
60767 |
50 |
0 |
0 |
T115 |
67653 |
70 |
0 |
0 |
T116 |
15552 |
16 |
0 |
0 |
T123 |
113620 |
819 |
0 |
0 |
T124 |
6963 |
7 |
0 |
0 |
T136 |
20412 |
91 |
0 |
0 |
T142 |
20746 |
87 |
0 |
0 |
T143 |
64110 |
50 |
0 |
0 |
T144 |
103312 |
116 |
0 |
0 |
T145 |
5586 |
5 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1478 |
0 |
0 |
T93 |
60767 |
26 |
0 |
0 |
T115 |
67653 |
87 |
0 |
0 |
T116 |
15552 |
19 |
0 |
0 |
T123 |
113620 |
848 |
0 |
0 |
T124 |
6963 |
16 |
0 |
0 |
T136 |
20412 |
66 |
0 |
0 |
T142 |
20746 |
76 |
0 |
0 |
T143 |
64110 |
44 |
0 |
0 |
T144 |
103312 |
95 |
0 |
0 |
T146 |
9541 |
12 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1468 |
0 |
0 |
T93 |
60767 |
43 |
0 |
0 |
T115 |
67653 |
83 |
0 |
0 |
T116 |
15552 |
26 |
0 |
0 |
T123 |
113620 |
784 |
0 |
0 |
T124 |
6963 |
4 |
0 |
0 |
T136 |
20412 |
84 |
0 |
0 |
T142 |
20746 |
76 |
0 |
0 |
T143 |
64110 |
26 |
0 |
0 |
T144 |
103312 |
125 |
0 |
0 |
T146 |
9541 |
14 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
2168 |
0 |
0 |
T93 |
60767 |
101 |
0 |
0 |
T115 |
67653 |
267 |
0 |
0 |
T116 |
15552 |
32 |
0 |
0 |
T123 |
113620 |
755 |
0 |
0 |
T124 |
6963 |
13 |
0 |
0 |
T136 |
20412 |
56 |
0 |
0 |
T142 |
20746 |
75 |
0 |
0 |
T143 |
64110 |
107 |
0 |
0 |
T144 |
103312 |
339 |
0 |
0 |
T146 |
9541 |
29 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1402 |
0 |
0 |
T93 |
60767 |
46 |
0 |
0 |
T115 |
67653 |
80 |
0 |
0 |
T116 |
15552 |
23 |
0 |
0 |
T123 |
113620 |
741 |
0 |
0 |
T124 |
6963 |
2 |
0 |
0 |
T136 |
20412 |
25 |
0 |
0 |
T142 |
20746 |
77 |
0 |
0 |
T143 |
64110 |
74 |
0 |
0 |
T144 |
103312 |
151 |
0 |
0 |
T145 |
5586 |
2 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
2260 |
0 |
0 |
T93 |
60767 |
114 |
0 |
0 |
T115 |
67653 |
234 |
0 |
0 |
T116 |
15552 |
32 |
0 |
0 |
T123 |
113620 |
795 |
0 |
0 |
T124 |
6963 |
49 |
0 |
0 |
T136 |
20412 |
76 |
0 |
0 |
T142 |
20746 |
17 |
0 |
0 |
T143 |
64110 |
125 |
0 |
0 |
T144 |
103312 |
310 |
0 |
0 |
T145 |
5586 |
2 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1690 |
0 |
0 |
T93 |
60767 |
68 |
0 |
0 |
T115 |
67653 |
121 |
0 |
0 |
T116 |
15552 |
47 |
0 |
0 |
T123 |
113620 |
784 |
0 |
0 |
T124 |
6963 |
14 |
0 |
0 |
T136 |
20412 |
108 |
0 |
0 |
T142 |
20746 |
40 |
0 |
0 |
T143 |
64110 |
69 |
0 |
0 |
T144 |
103312 |
146 |
0 |
0 |
T145 |
5586 |
8 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1375 |
0 |
0 |
T93 |
60767 |
55 |
0 |
0 |
T115 |
67653 |
73 |
0 |
0 |
T116 |
15552 |
31 |
0 |
0 |
T123 |
113620 |
760 |
0 |
0 |
T124 |
6963 |
5 |
0 |
0 |
T136 |
20412 |
77 |
0 |
0 |
T142 |
20746 |
31 |
0 |
0 |
T143 |
64110 |
27 |
0 |
0 |
T144 |
103312 |
130 |
0 |
0 |
T145 |
5586 |
1 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1448 |
0 |
0 |
T93 |
60767 |
52 |
0 |
0 |
T115 |
67653 |
91 |
0 |
0 |
T116 |
15552 |
19 |
0 |
0 |
T123 |
113620 |
813 |
0 |
0 |
T124 |
6963 |
12 |
0 |
0 |
T136 |
20412 |
71 |
0 |
0 |
T142 |
20746 |
47 |
0 |
0 |
T143 |
64110 |
36 |
0 |
0 |
T144 |
103312 |
121 |
0 |
0 |
T145 |
5586 |
1 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1507 |
0 |
0 |
T93 |
60767 |
46 |
0 |
0 |
T115 |
67653 |
106 |
0 |
0 |
T116 |
15552 |
28 |
0 |
0 |
T123 |
113620 |
819 |
0 |
0 |
T124 |
6963 |
12 |
0 |
0 |
T136 |
20412 |
63 |
0 |
0 |
T142 |
20746 |
81 |
0 |
0 |
T143 |
64110 |
43 |
0 |
0 |
T144 |
103312 |
89 |
0 |
0 |
T146 |
9541 |
13 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1325 |
0 |
0 |
T93 |
60767 |
23 |
0 |
0 |
T115 |
67653 |
70 |
0 |
0 |
T116 |
15552 |
26 |
0 |
0 |
T123 |
113620 |
746 |
0 |
0 |
T124 |
6963 |
14 |
0 |
0 |
T136 |
20412 |
34 |
0 |
0 |
T142 |
20746 |
38 |
0 |
0 |
T143 |
64110 |
49 |
0 |
0 |
T144 |
103312 |
119 |
0 |
0 |
T145 |
5586 |
6 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1410 |
0 |
0 |
T93 |
60767 |
48 |
0 |
0 |
T115 |
67653 |
86 |
0 |
0 |
T116 |
15552 |
24 |
0 |
0 |
T123 |
113620 |
848 |
0 |
0 |
T124 |
6963 |
10 |
0 |
0 |
T136 |
20412 |
35 |
0 |
0 |
T142 |
20746 |
74 |
0 |
0 |
T143 |
64110 |
28 |
0 |
0 |
T144 |
103312 |
93 |
0 |
0 |
T145 |
5586 |
7 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462638574 |
1426 |
0 |
0 |
T93 |
60767 |
31 |
0 |
0 |
T100 |
17734 |
1 |
0 |
0 |
T115 |
67653 |
91 |
0 |
0 |
T116 |
15552 |
20 |
0 |
0 |
T123 |
113620 |
797 |
0 |
0 |
T124 |
6963 |
3 |
0 |
0 |
T136 |
20412 |
61 |
0 |
0 |
T142 |
20746 |
98 |
0 |
0 |
T143 |
64110 |
46 |
0 |
0 |
T144 |
103312 |
109 |
0 |
0 |