Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3870369	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4295096

1

T1

6964

T2

1595

T3

6459

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4525977	1			T1	3089		T2	1389		T3	5871
values[0x0]	1820395	1			T1	2656		T2	425		T3	3248
values[0x1]	1819093	1			T1	2639		T2	465		T3	3260

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2729804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5435661

1

T1

7283

T2

1734

T3

8078

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29020	1			T1	1		T2	10		T3	47
valid_sources[0x01]	32451	1			T1	25		T2	7		T3	46
valid_sources[0x02]	29391	1			T1	28		T2	11		T3	38
valid_sources[0x03]	32586	1			T1	22		T2	20		T3	55
valid_sources[0x04]	30097	1			T1	6		T2	4		T3	49
valid_sources[0x05]	31826	1			T1	38		T2	11		T3	34
valid_sources[0x06]	31191	1			T1	25		T2	4		T3	49
valid_sources[0x07]	29119	1			T1	5		T2	8		T3	44
valid_sources[0x08]	28873	1			T1	50		T2	8		T3	48
valid_sources[0x09]	27076	1			T1	21		T2	9		T3	43
valid_sources[0x0a]	28463	1			T2	7		T3	44		T6	5
valid_sources[0x0b]	34133	1			T1	13		T2	12		T3	42
valid_sources[0x0c]	30140	1			T1	28		T2	12		T3	43
valid_sources[0x0d]	29366	1			T1	39		T2	16		T3	44
valid_sources[0x0e]	30652	1			T1	69		T2	7		T3	55
valid_sources[0x0f]	30146	1			T1	30		T2	4		T3	49
valid_sources[0x10]	33062	1			T1	9		T2	10		T3	47
valid_sources[0x11]	31071	1			T1	64		T2	8		T3	52
valid_sources[0x12]	29890	1			T1	19		T2	13		T3	50
valid_sources[0x13]	33067	1			T1	13		T2	9		T3	49
valid_sources[0x14]	28848	1			T1	33		T2	14		T3	55
valid_sources[0x15]	29928	1			T1	30		T2	8		T3	45
valid_sources[0x16]	30547	1			T1	20		T2	7		T3	62
valid_sources[0x17]	33242	1			T1	33		T2	6		T3	41
valid_sources[0x18]	32283	1			T1	32		T2	10		T3	45
valid_sources[0x19]	38820	1			T1	60		T2	7		T3	43
valid_sources[0x1a]	32282	1			T1	12		T2	11		T3	53
valid_sources[0x1b]	29494	1			T1	74		T2	12		T3	57
valid_sources[0x1c]	40035	1			T1	17		T2	3		T3	45
valid_sources[0x1d]	31239	1			T1	42		T2	15		T3	33
valid_sources[0x1e]	32362	1			T1	18		T2	12		T3	44
valid_sources[0x1f]	30986	1			T1	62		T2	12		T3	49
valid_sources[0x20]	29664	1			T1	32		T2	12		T3	39
valid_sources[0x21]	32336	1			T1	29		T2	8		T3	52
valid_sources[0x22]	56209	1			T1	17		T2	9		T3	47
valid_sources[0x23]	31009	1			T1	5		T2	6		T3	48
valid_sources[0x24]	32631	1			T1	29		T2	4		T3	40
valid_sources[0x25]	31993	1			T1	50		T2	9		T3	51
valid_sources[0x26]	30846	1			T1	8		T2	7		T3	40
valid_sources[0x27]	35169	1			T1	67		T2	8		T3	52
valid_sources[0x28]	31556	1			T1	32		T2	8		T3	49
valid_sources[0x29]	34753	1			T1	1		T2	11		T3	37
valid_sources[0x2a]	29075	1			T1	39		T2	8		T3	38
valid_sources[0x2b]	30087	1			T1	50		T2	9		T3	55
valid_sources[0x2c]	29815	1			T1	39		T2	11		T3	58
valid_sources[0x2d]	39004	1			T1	7		T2	11		T3	59
valid_sources[0x2e]	30692	1			T1	5		T2	6		T3	53
valid_sources[0x2f]	30696	1			T1	38		T2	10		T3	50
valid_sources[0x30]	34856	1			T1	68		T2	8		T3	41
valid_sources[0x31]	30626	1			T1	13		T2	5		T3	48
valid_sources[0x32]	27734	1			T1	23		T2	7		T3	46
valid_sources[0x33]	31994	1			T1	133		T2	6		T3	46
valid_sources[0x34]	31573	1			T1	24		T2	5		T3	33
valid_sources[0x35]	31530	1			T1	5		T2	12		T3	44
valid_sources[0x36]	29633	1			T1	82		T2	10		T3	45
valid_sources[0x37]	31983	1			T1	47		T2	9		T3	56
valid_sources[0x38]	30447	1			T1	23		T2	10		T3	42
valid_sources[0x39]	36747	1			T1	153		T2	11		T3	37
valid_sources[0x3a]	29200	1			T1	11		T2	16		T3	43
valid_sources[0x3b]	33133	1			T1	47		T2	5		T3	57
valid_sources[0x3c]	29116	1			T1	22		T2	6		T3	38
valid_sources[0x3d]	31618	1			T1	87		T2	10		T3	46
valid_sources[0x3e]	29520	1			T1	8		T2	3		T3	50
valid_sources[0x3f]	29382	1			T1	21		T2	12		T3	45
valid_sources[0x40]	31979	1			T1	51		T2	5		T3	50
valid_sources[0x41]	33188	1			T2	3		T3	50		T6	25
valid_sources[0x42]	31339	1			T1	23		T2	8		T3	39
valid_sources[0x43]	29709	1			T1	37		T2	8		T3	56
valid_sources[0x44]	32972	1			T1	19		T2	11		T3	41
valid_sources[0x45]	29618	1			T1	23		T2	7		T3	57
valid_sources[0x46]	28746	1			T1	29		T2	9		T3	42
valid_sources[0x47]	38558	1			T1	48		T2	8		T3	57
valid_sources[0x48]	30421	1			T1	27		T2	5		T3	52
valid_sources[0x49]	41338	1			T1	89		T2	6		T3	56
valid_sources[0x4a]	32993	1			T1	6		T2	11		T3	46
valid_sources[0x4b]	32701	1			T1	43		T2	9		T3	48
valid_sources[0x4c]	30328	1			T1	25		T2	15		T3	34
valid_sources[0x4d]	34760	1			T1	11		T2	14		T3	43
valid_sources[0x4e]	32531	1			T1	41		T2	18		T3	55
valid_sources[0x4f]	32756	1			T1	12		T2	1		T3	42
valid_sources[0x50]	30987	1			T1	22		T2	7		T3	37
valid_sources[0x51]	30381	1			T1	32		T2	8		T3	49
valid_sources[0x52]	33501	1			T1	11		T2	5		T3	61
valid_sources[0x53]	29325	1			T1	7		T2	6		T3	42
valid_sources[0x54]	33247	1			T1	43		T2	10		T3	39
valid_sources[0x55]	31875	1			T2	9		T3	64		T6	11
valid_sources[0x56]	29079	1			T1	100		T2	7		T3	56
valid_sources[0x57]	29962	1			T1	3		T2	4		T3	56
valid_sources[0x58]	30310	1			T1	18		T2	5		T3	44
valid_sources[0x59]	32150	1			T1	14		T2	4		T3	55
valid_sources[0x5a]	30927	1			T1	8		T2	6		T3	50
valid_sources[0x5b]	30036	1			T1	27		T2	11		T3	48
valid_sources[0x5c]	30391	1			T1	40		T2	12		T3	40
valid_sources[0x5d]	38071	1			T1	12		T2	8		T3	56
valid_sources[0x5e]	31469	1			T1	34		T2	8		T3	56
valid_sources[0x5f]	30512	1			T1	35		T2	12		T3	55
valid_sources[0x60]	37632	1			T1	56		T2	7		T3	48
valid_sources[0x61]	28654	1			T2	6		T3	57		T4	1
valid_sources[0x62]	31782	1			T1	70		T2	12		T3	40
valid_sources[0x63]	29328	1			T1	63		T2	6		T3	61
valid_sources[0x64]	29153	1			T1	53		T2	8		T3	62
valid_sources[0x65]	30947	1			T1	89		T2	8		T3	46
valid_sources[0x66]	41442	1			T1	18		T2	8		T3	49
valid_sources[0x67]	30741	1			T1	46		T2	4		T3	55
valid_sources[0x68]	31749	1			T1	43		T2	9		T3	52
valid_sources[0x69]	30587	1			T1	30		T2	16		T3	52
valid_sources[0x6a]	29269	1			T1	13		T2	8		T3	50
valid_sources[0x6b]	33534	1			T1	76		T2	8		T3	41
valid_sources[0x6c]	49795	1			T1	85		T2	9		T3	54
valid_sources[0x6d]	30269	1			T1	37		T2	16		T3	57
valid_sources[0x6e]	30554	1			T1	6		T2	7		T3	45
valid_sources[0x6f]	30289	1			T1	56		T2	6		T3	55
valid_sources[0x70]	27427	1			T1	11		T2	11		T3	34
valid_sources[0x71]	34058	1			T1	30		T2	9		T3	51
valid_sources[0x72]	33852	1			T1	34		T2	2		T3	47
valid_sources[0x73]	28467	1			T1	58		T2	4		T3	47
valid_sources[0x74]	30642	1			T1	43		T2	6		T3	64
valid_sources[0x75]	33280	1			T2	11		T3	44		T4	2
valid_sources[0x76]	36161	1			T1	57		T2	8		T3	43
valid_sources[0x77]	32012	1			T1	34		T2	8		T3	54
valid_sources[0x78]	27946	1			T1	21		T2	7		T3	46
valid_sources[0x79]	29658	1			T1	45		T2	12		T3	56
valid_sources[0x7a]	29204	1			T1	16		T2	8		T3	58
valid_sources[0x7b]	29276	1			T1	49		T2	10		T3	47
valid_sources[0x7c]	27873	1			T1	52		T2	9		T3	52
valid_sources[0x7d]	31940	1			T1	46		T2	10		T3	50
valid_sources[0x7e]	32889	1			T1	22		T2	14		T3	49
valid_sources[0x7f]	33131	1			T1	3		T2	7		T3	49
valid_sources[0x80]	36026	1			T1	31		T2	10		T3	47

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1014812

1

T1

1698

T2

709

T3

1414

values[0x0]

all_enables

biggest_size

1653765

1

T1

2651

T2

425

T3

2590

values[0x1]

all_enables

biggest_size

1626519

1

T1

2615

T2

461

T3

2455