Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3891525

1

T1

1420

T2

684

T3

5920

full_word

4294226

1

T1

6964

T2

1595

T3

6459

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8185421	1			T1	8384		T2	2279		T3	12379
auto[TlIntgErrCmd]	110	1			T102	9		T103	4		T104	9
auto[TlIntgErrData]	107	1			T102	4		T103	4		T104	8
auto[TlIntgErrBoth]	113	1			T102	7		T103	2		T104	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4527759

1

T1

3089

T2

1389

T3

5871

auto[1]

3657992

1

T1

5295

T2

890

T3

6508

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3512682	1			T1	1391		T2	680		T3	4457
auto[TlIntgErrNone]	partial	auto[1]	378544	1			T1	29		T2	4		T3	1463
auto[TlIntgErrNone]	full_word	auto[0]	1014915	1			T1	1698		T2	709		T3	1414
auto[TlIntgErrNone]	full_word	auto[1]	3279280	1			T1	5266		T2	886		T3	5045
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T102	4		T103	1		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T102	5		T103	3		T104	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T104	1		T170	1		T171	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T170	1		T169	1		-	-
auto[TlIntgErrData]	partial	auto[0]	56	1			T102	1		T103	3		T104	4
auto[TlIntgErrData]	partial	auto[1]	40	1			T102	3		T103	1		T104	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T170	1		T164	1		T172	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T173	1		T164	1		T169	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T102	2		T104	9		T170	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T102	4		T103	2		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T102	1		T170	1		T174	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T104	1		T170	1		T175	1