Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473445271	2845826	0	0
DepthKnown_A	473445271	473316266	0	0
RvalidKnown_A	473445271	473316266	0	0
WreadyKnown_A	473445271	473316266	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	2845826	0	0
T1	186625	4992	0	0
T2	939168	1663	0	0
T3	364993	2495	0	0
T4	1308	0	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	1663	0	0
T8	159181	12481	0	0
T9	149222	1663	0	0
T10	193951	832	0	0
T11	0	832	0	0
T12	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473445271	3094147	0	0
DepthKnown_A	473445271	473316266	0	0
RvalidKnown_A	473445271	473316266	0	0
WreadyKnown_A	473445271	473316266	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	3094147	0	0
T1	186625	4992	0	0
T2	939168	832	0	0
T3	364993	1664	0	0
T4	1308	0	0	0
T5	1288	0	0	0
T6	48648	2663	0	0
T7	7121	832	0	0
T8	159181	17080	0	0
T9	149222	832	0	0
T10	193951	832	0	0
T11	0	832	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473445271	189903	0	0
DepthKnown_A	473445271	473316266	0	0
RvalidKnown_A	473445271	473316266	0	0
WreadyKnown_A	473445271	473316266	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	189903	0	0
T1	186625	384	0	0
T2	939168	0	0	0
T3	364993	1083	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	0	0	0
T7	7121	0	0	0
T8	159181	681	0	0
T9	149222	0	0	0
T10	193951	128	0	0
T13	0	802	0	0
T23	0	128	0	0
T24	0	100	0	0
T25	0	1269	0	0
T30	0	301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473445271	415552	0	0
DepthKnown_A	473445271	473316266	0	0
RvalidKnown_A	473445271	473316266	0	0
WreadyKnown_A	473445271	473316266	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	415552	0	0
T1	186625	384	0	0
T2	939168	0	0	0
T3	364993	1083	0	0
T4	1308	4	0	0
T5	1288	0	0	0
T6	48648	0	0	0
T7	7121	0	0	0
T8	159181	2155	0	0
T9	149222	0	0	0
T10	193951	128	0	0
T13	0	2526	0	0
T23	0	128	0	0
T24	0	100	0	0
T25	0	1269	0	0
T30	0	301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473445271	6524584	0	0
DepthKnown_A	473445271	473316266	0	0
RvalidKnown_A	473445271	473316266	0	0
WreadyKnown_A	473445271	473316266	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	6524584	0	0
T1	186625	3011	0	0
T2	939168	1447	0	0
T3	364993	9680	0	0
T4	1308	35	0	0
T5	1288	6	0	0
T6	48648	1870	0	0
T7	7121	47	0	0
T8	159181	14832	0	0
T9	149222	4176	0	0
T10	193951	407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473445271	13303834	0	0
DepthKnown_A	473445271	473316266	0	0
RvalidKnown_A	473445271	473316266	0	0
WreadyKnown_A	473445271	473316266	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	13303834	0	0
T1	186625	3008	0	0
T2	939168	1447	0	0
T3	364993	9632	0	0
T4	1308	89	0	0
T5	1288	6	0	0
T6	48648	5929	0	0
T7	7121	47	0	0
T8	159181	43850	0	0
T9	149222	18069	0	0
T10	193951	407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473445271	473316266	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0