Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T8,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Unreachable
1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	759165952	613939648	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	759165952	3694417	0	0
GntImpliesValid_A	759165952	3694417	0	0
GrantKnown_A	759165952	613939648	0	0
IdxKnown_A	759165952	613939648	0	0
IndexIsCorrect_A	759165952	3694417	0	0
LockArbDecision_A	759165952	0	0	0
NoReadyValidNoGrant_A	759165952	0	0	0
ReadyAndValidImplyGrant_A	759165952	3694417	0	0
ReqAndReadyImplyGrant_A	759165952	3694417	0	0
ReqImpliesValid_A	759165952	3694417	0	0
ReqStaysHighUntilGranted0_M	759165952	0	0	0
RoundRobin_A	759165952	3	0	976
ValidKnown_A	759165952	613939648	0	0
gen_data_port_assertion.DataFlow_A	759165952	3694417	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	613939648	0	0
T1	801953	800140	0	0
T2	1056084	1055988	0	0
T3	1029877	690978	0	0
T4	1404	1286	0	0
T5	1288	1226	0	0
T6	311686	179548	0	0
T7	8735	7862	0	0
T8	923175	537974	0	0
T9	440246	294637	0	0
T10	375995	284413	0	0
T11	34676	17338	0	0
T12	30100	30100	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3694417	0	0
T1	801953	16999	0	0
T2	1056084	832	0	0
T3	1029877	10698	0	0
T4	1404	2	0	0
T5	1288	0	0	0
T6	311686	832	0	0
T7	8735	832	0	0
T8	923175	15127	0	0
T9	440246	832	0	0
T10	375995	6862	0	0
T11	34676	832	0	0
T12	30100	0	0	0
T13	266056	5059	0	0
T23	0	3969	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	16880	0	0
T34	0	107	0	0
T39	0	731	0	0
T41	0	265	0	0
T43	0	3047	0	0
T54	0	436	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3694417	0	0
T1	801953	16999	0	0
T2	1056084	832	0	0
T3	1029877	10698	0	0
T4	1404	2	0	0
T5	1288	0	0	0
T6	311686	832	0	0
T7	8735	832	0	0
T8	923175	15127	0	0
T9	440246	832	0	0
T10	375995	6862	0	0
T11	34676	832	0	0
T12	30100	0	0	0
T13	266056	5059	0	0
T23	0	3969	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	16880	0	0
T34	0	107	0	0
T39	0	731	0	0
T41	0	265	0	0
T43	0	3047	0	0
T54	0	436	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	613939648	0	0
T1	801953	800140	0	0
T2	1056084	1055988	0	0
T3	1029877	690978	0	0
T4	1404	1286	0	0
T5	1288	1226	0	0
T6	311686	179548	0	0
T7	8735	7862	0	0
T8	923175	537974	0	0
T9	440246	294637	0	0
T10	375995	284413	0	0
T11	34676	17338	0	0
T12	30100	30100	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	613939648	0	0
T1	801953	800140	0	0
T2	1056084	1055988	0	0
T3	1029877	690978	0	0
T4	1404	1286	0	0
T5	1288	1226	0	0
T6	311686	179548	0	0
T7	8735	7862	0	0
T8	923175	537974	0	0
T9	440246	294637	0	0
T10	375995	284413	0	0
T11	34676	17338	0	0
T12	30100	30100	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3694417	0	0
T1	801953	16999	0	0
T2	1056084	832	0	0
T3	1029877	10698	0	0
T4	1404	2	0	0
T5	1288	0	0	0
T6	311686	832	0	0
T7	8735	832	0	0
T8	923175	15127	0	0
T9	440246	832	0	0
T10	375995	6862	0	0
T11	34676	832	0	0
T12	30100	0	0	0
T13	266056	5059	0	0
T23	0	3969	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	16880	0	0
T34	0	107	0	0
T39	0	731	0	0
T41	0	265	0	0
T43	0	3047	0	0
T54	0	436	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3694417	0	0
T1	801953	16999	0	0
T2	1056084	832	0	0
T3	1029877	10698	0	0
T4	1404	2	0	0
T5	1288	0	0	0
T6	311686	832	0	0
T7	8735	832	0	0
T8	923175	15127	0	0
T9	440246	832	0	0
T10	375995	6862	0	0
T11	34676	832	0	0
T12	30100	0	0	0
T13	266056	5059	0	0
T23	0	3969	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	16880	0	0
T34	0	107	0	0
T39	0	731	0	0
T41	0	265	0	0
T43	0	3047	0	0
T54	0	436	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3694417	0	0
T1	801953	16999	0	0
T2	1056084	832	0	0
T3	1029877	10698	0	0
T4	1404	2	0	0
T5	1288	0	0	0
T6	311686	832	0	0
T7	8735	832	0	0
T8	923175	15127	0	0
T9	440246	832	0	0
T10	375995	6862	0	0
T11	34676	832	0	0
T12	30100	0	0	0
T13	266056	5059	0	0
T23	0	3969	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	16880	0	0
T34	0	107	0	0
T39	0	731	0	0
T41	0	265	0	0
T43	0	3047	0	0
T54	0	436	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3694417	0	0
T1	801953	16999	0	0
T2	1056084	832	0	0
T3	1029877	10698	0	0
T4	1404	2	0	0
T5	1288	0	0	0
T6	311686	832	0	0
T7	8735	832	0	0
T8	923175	15127	0	0
T9	440246	832	0	0
T10	375995	6862	0	0
T11	34676	832	0	0
T12	30100	0	0	0
T13	266056	5059	0	0
T23	0	3969	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	16880	0	0
T34	0	107	0	0
T39	0	731	0	0
T41	0	265	0	0
T43	0	3047	0	0
T54	0	436	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3	0	976
T55	441026	1	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	165030	0	0	1
T59	111407	0	0	1
T60	22029	0	0	1
T61	852	0	0	1
T62	1173	0	0	1
T63	178043	0	0	1
T64	345694	0	0	1
T65	427393	0	0	1
T66	826	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	613939648	0	0
T1	801953	800140	0	0
T2	1056084	1055988	0	0
T3	1029877	690978	0	0
T4	1404	1286	0	0
T5	1288	1226	0	0
T6	311686	179548	0	0
T7	8735	7862	0	0
T8	923175	537974	0	0
T9	440246	294637	0	0
T10	375995	284413	0	0
T11	34676	17338	0	0
T12	30100	30100	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759165952	3694417	0	0
T1	801953	16999	0	0
T2	1056084	832	0	0
T3	1029877	10698	0	0
T4	1404	2	0	0
T5	1288	0	0	0
T6	311686	832	0	0
T7	8735	832	0	0
T8	923175	15127	0	0
T9	440246	832	0	0
T10	375995	6862	0	0
T11	34676	832	0	0
T12	30100	0	0	0
T13	266056	5059	0	0
T23	0	3969	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	16880	0	0
T34	0	107	0	0
T39	0	731	0	0
T41	0	265	0	0
T43	0	3047	0	0
T54	0	436	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T8,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Unreachable
1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143828559	25871427	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	143828559	624548	0	0
GntImpliesValid_A	143828559	624548	0	0
GrantKnown_A	143828559	25871427	0	0
IdxKnown_A	143828559	25871427	0	0
IndexIsCorrect_A	143828559	624548	0	0
LockArbDecision_A	143828559	0	0	0
NoReadyValidNoGrant_A	143828559	0	0	0
ReadyAndValidImplyGrant_A	143828559	624548	0	0
ReqAndReadyImplyGrant_A	143828559	624548	0	0
ReqImpliesValid_A	143828559	624548	0	0
ReqStaysHighUntilGranted0_M	143828559	0	0	0
RoundRobin_A	143828559	0	0	0
ValidKnown_A	143828559	25871427	0	0
gen_data_port_assertion.DataFlow_A	143828559	624548	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	25871427	0	0
T3	332442	239304	0	0
T4	48	48	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	31624	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	624548	0	0
T3	332442	6145	0	0
T4	48	1	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	1284	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	5057	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	3495	0	0
T34	0	107	0	0
T43	0	3047	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	624548	0	0
T3	332442	6145	0	0
T4	48	1	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	1284	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	5057	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	3495	0	0
T34	0	107	0	0
T43	0	3047	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	25871427	0	0
T3	332442	239304	0	0
T4	48	48	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	31624	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	25871427	0	0
T3	332442	239304	0	0
T4	48	48	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	31624	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	624548	0	0
T3	332442	6145	0	0
T4	48	1	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	1284	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	5057	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	3495	0	0
T34	0	107	0	0
T43	0	3047	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	624548	0	0
T3	332442	6145	0	0
T4	48	1	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	1284	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	5057	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	3495	0	0
T34	0	107	0	0
T43	0	3047	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	624548	0	0
T3	332442	6145	0	0
T4	48	1	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	1284	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	5057	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	3495	0	0
T34	0	107	0	0
T43	0	3047	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	624548	0	0
T3	332442	6145	0	0
T4	48	1	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	1284	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	5057	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	3495	0	0
T34	0	107	0	0
T43	0	3047	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	25871427	0	0
T3	332442	239304	0	0
T4	48	48	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	31624	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	152512	0	0
T25	0	175960	0	0
T27	0	59096	0	0
T30	0	41888	0	0
T31	0	28536	0	0
T32	0	104976	0	0
T33	0	317224	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	624548	0	0
T3	332442	6145	0	0
T4	48	1	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	1284	0	0
T9	145512	0	0	0
T10	91022	0	0	0
T11	17338	0	0	0
T12	30100	0	0	0
T13	266056	5057	0	0
T25	0	7309	0	0
T30	0	1664	0	0
T32	0	1138	0	0
T33	0	3495	0	0
T34	0	107	0	0
T43	0	3047	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143828559	116648910	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	143828559	844157	0	0
GntImpliesValid_A	143828559	844157	0	0
GrantKnown_A	143828559	116648910	0	0
IdxKnown_A	143828559	116648910	0	0
IndexIsCorrect_A	143828559	844157	0	0
LockArbDecision_A	143828559	0	0	0
NoReadyValidNoGrant_A	143828559	0	0	0
ReadyAndValidImplyGrant_A	143828559	844157	0	0
ReqAndReadyImplyGrant_A	143828559	844157	0	0
ReqImpliesValid_A	143828559	844157	0	0
ReqStaysHighUntilGranted0_M	143828559	0	0	0
RoundRobin_A	143828559	0	0	0
ValidKnown_A	143828559	116648910	0	0
gen_data_port_assertion.DataFlow_A	143828559	844157	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	116648910	0	0
T1	615328	613520	0	0
T2	116916	116916	0	0
T3	332442	86737	0	0
T4	48	0	0	0
T6	131519	130954	0	0
T7	807	807	0	0
T8	381997	347176	0	0
T9	145512	145512	0	0
T10	91022	90540	0	0
T11	17338	17338	0	0
T12	0	30100	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	844157	0	0
T1	615328	11605	0	0
T2	116916	0	0	0
T3	332442	6	0	0
T4	48	0	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	4368	0	0
T9	145512	0	0	0
T10	91022	5898	0	0
T11	17338	0	0	0
T13	0	2	0	0
T23	0	3969	0	0
T33	0	13385	0	0
T39	0	731	0	0
T41	0	265	0	0
T54	0	436	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	844157	0	0
T1	615328	11605	0	0
T2	116916	0	0	0
T3	332442	6	0	0
T4	48	0	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	4368	0	0
T9	145512	0	0	0
T10	91022	5898	0	0
T11	17338	0	0	0
T13	0	2	0	0
T23	0	3969	0	0
T33	0	13385	0	0
T39	0	731	0	0
T41	0	265	0	0
T54	0	436	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	116648910	0	0
T1	615328	613520	0	0
T2	116916	116916	0	0
T3	332442	86737	0	0
T4	48	0	0	0
T6	131519	130954	0	0
T7	807	807	0	0
T8	381997	347176	0	0
T9	145512	145512	0	0
T10	91022	90540	0	0
T11	17338	17338	0	0
T12	0	30100	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	116648910	0	0
T1	615328	613520	0	0
T2	116916	116916	0	0
T3	332442	86737	0	0
T4	48	0	0	0
T6	131519	130954	0	0
T7	807	807	0	0
T8	381997	347176	0	0
T9	145512	145512	0	0
T10	91022	90540	0	0
T11	17338	17338	0	0
T12	0	30100	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	844157	0	0
T1	615328	11605	0	0
T2	116916	0	0	0
T3	332442	6	0	0
T4	48	0	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	4368	0	0
T9	145512	0	0	0
T10	91022	5898	0	0
T11	17338	0	0	0
T13	0	2	0	0
T23	0	3969	0	0
T33	0	13385	0	0
T39	0	731	0	0
T41	0	265	0	0
T54	0	436	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	844157	0	0
T1	615328	11605	0	0
T2	116916	0	0	0
T3	332442	6	0	0
T4	48	0	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	4368	0	0
T9	145512	0	0	0
T10	91022	5898	0	0
T11	17338	0	0	0
T13	0	2	0	0
T23	0	3969	0	0
T33	0	13385	0	0
T39	0	731	0	0
T41	0	265	0	0
T54	0	436	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	844157	0	0
T1	615328	11605	0	0
T2	116916	0	0	0
T3	332442	6	0	0
T4	48	0	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	4368	0	0
T9	145512	0	0	0
T10	91022	5898	0	0
T11	17338	0	0	0
T13	0	2	0	0
T23	0	3969	0	0
T33	0	13385	0	0
T39	0	731	0	0
T41	0	265	0	0
T54	0	436	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	844157	0	0
T1	615328	11605	0	0
T2	116916	0	0	0
T3	332442	6	0	0
T4	48	0	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	4368	0	0
T9	145512	0	0	0
T10	91022	5898	0	0
T11	17338	0	0	0
T13	0	2	0	0
T23	0	3969	0	0
T33	0	13385	0	0
T39	0	731	0	0
T41	0	265	0	0
T54	0	436	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	116648910	0	0
T1	615328	613520	0	0
T2	116916	116916	0	0
T3	332442	86737	0	0
T4	48	0	0	0
T6	131519	130954	0	0
T7	807	807	0	0
T8	381997	347176	0	0
T9	145512	145512	0	0
T10	91022	90540	0	0
T11	17338	17338	0	0
T12	0	30100	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143828559	844157	0	0
T1	615328	11605	0	0
T2	116916	0	0	0
T3	332442	6	0	0
T4	48	0	0	0
T6	131519	0	0	0
T7	807	0	0	0
T8	381997	4368	0	0
T9	145512	0	0	0
T10	91022	5898	0	0
T11	17338	0	0	0
T13	0	2	0	0
T23	0	3969	0	0
T33	0	13385	0	0
T39	0	731	0	0
T41	0	265	0	0
T54	0	436	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	471508834	471419311	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	471508834	2225712	0	0
GntImpliesValid_A	471508834	2225712	0	0
GrantKnown_A	471508834	471419311	0	0
IdxKnown_A	471508834	471419311	0	0
IndexIsCorrect_A	471508834	2225712	0	0
LockArbDecision_A	471508834	0	0	0
NoReadyValidNoGrant_A	471508834	0	0	0
ReadyAndValidImplyGrant_A	471508834	2225712	0	0
ReqAndReadyImplyGrant_A	471508834	2225712	0	0
ReqImpliesValid_A	471508834	2225712	0	0
ReqStaysHighUntilGranted0_M	471508834	0	0	0
RoundRobin_A	471508834	3	0	976
ValidKnown_A	471508834	471419311	0	0
gen_data_port_assertion.DataFlow_A	471508834	2225712	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	471419311	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	2225712	0	0
T1	186625	5394	0	0
T2	939168	832	0	0
T3	364993	4547	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	832	0	0
T8	159181	9475	0	0
T9	149222	832	0	0
T10	193951	964	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	2225712	0	0
T1	186625	5394	0	0
T2	939168	832	0	0
T3	364993	4547	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	832	0	0
T8	159181	9475	0	0
T9	149222	832	0	0
T10	193951	964	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	471419311	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	471419311	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	2225712	0	0
T1	186625	5394	0	0
T2	939168	832	0	0
T3	364993	4547	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	832	0	0
T8	159181	9475	0	0
T9	149222	832	0	0
T10	193951	964	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	2225712	0	0
T1	186625	5394	0	0
T2	939168	832	0	0
T3	364993	4547	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	832	0	0
T8	159181	9475	0	0
T9	149222	832	0	0
T10	193951	964	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	2225712	0	0
T1	186625	5394	0	0
T2	939168	832	0	0
T3	364993	4547	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	832	0	0
T8	159181	9475	0	0
T9	149222	832	0	0
T10	193951	964	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	2225712	0	0
T1	186625	5394	0	0
T2	939168	832	0	0
T3	364993	4547	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	832	0	0
T8	159181	9475	0	0
T9	149222	832	0	0
T10	193951	964	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	3	0	976
T55	441026	1	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	165030	0	0	1
T59	111407	0	0	1
T60	22029	0	0	1
T61	852	0	0	1
T62	1173	0	0	1
T63	178043	0	0	1
T64	345694	0	0	1
T65	427393	0	0	1
T66	826	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	471419311	0	0
T1	186625	186620	0	0
T2	939168	939072	0	0
T3	364993	364937	0	0
T4	1308	1238	0	0
T5	1288	1226	0	0
T6	48648	48594	0	0
T7	7121	7055	0	0
T8	159181	159174	0	0
T9	149222	149125	0	0
T10	193951	193873	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471508834	2225712	0	0
T1	186625	5394	0	0
T2	939168	832	0	0
T3	364993	4547	0	0
T4	1308	1	0	0
T5	1288	0	0	0
T6	48648	832	0	0
T7	7121	832	0	0
T8	159181	9475	0	0
T9	149222	832	0	0
T10	193951	964	0	0
T11	0	832	0	0