Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3502 |
0 |
0 |
T99 |
3212 |
63 |
0 |
0 |
T100 |
6371 |
342 |
0 |
0 |
T101 |
14799 |
170 |
0 |
0 |
T102 |
55047 |
1 |
0 |
0 |
T103 |
34022 |
1 |
0 |
0 |
T105 |
18479 |
285 |
0 |
0 |
T106 |
7020 |
213 |
0 |
0 |
T109 |
6984 |
81 |
0 |
0 |
T113 |
12297 |
6 |
0 |
0 |
T115 |
3360 |
14 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1251 |
0 |
0 |
T85 |
2331 |
3 |
0 |
0 |
T87 |
3696 |
8 |
0 |
0 |
T89 |
4711 |
17 |
0 |
0 |
T103 |
34022 |
28 |
0 |
0 |
T116 |
6511 |
5 |
0 |
0 |
T119 |
10133 |
5 |
0 |
0 |
T123 |
10063 |
8 |
0 |
0 |
T155 |
17141 |
7 |
0 |
0 |
T156 |
14247 |
75 |
0 |
0 |
T157 |
10444 |
12 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1382 |
0 |
0 |
T85 |
2331 |
7 |
0 |
0 |
T87 |
3696 |
17 |
0 |
0 |
T103 |
34022 |
37 |
0 |
0 |
T116 |
6511 |
12 |
0 |
0 |
T119 |
10133 |
3 |
0 |
0 |
T123 |
10063 |
1 |
0 |
0 |
T124 |
5755 |
10 |
0 |
0 |
T155 |
17141 |
28 |
0 |
0 |
T156 |
14247 |
49 |
0 |
0 |
T157 |
10444 |
11 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1513 |
0 |
0 |
T85 |
2331 |
3 |
0 |
0 |
T87 |
3696 |
1 |
0 |
0 |
T103 |
34022 |
100 |
0 |
0 |
T116 |
6511 |
15 |
0 |
0 |
T119 |
10133 |
5 |
0 |
0 |
T123 |
10063 |
23 |
0 |
0 |
T124 |
5755 |
8 |
0 |
0 |
T155 |
17141 |
27 |
0 |
0 |
T156 |
14247 |
38 |
0 |
0 |
T157 |
10444 |
27 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
7502 |
0 |
0 |
T85 |
2331 |
6 |
0 |
0 |
T87 |
3696 |
5 |
0 |
0 |
T103 |
34022 |
602 |
0 |
0 |
T116 |
6511 |
13 |
0 |
0 |
T119 |
10133 |
274 |
0 |
0 |
T123 |
10063 |
73 |
0 |
0 |
T124 |
5755 |
7 |
0 |
0 |
T155 |
17141 |
288 |
0 |
0 |
T156 |
14247 |
11 |
0 |
0 |
T157 |
10444 |
129 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
6638 |
0 |
0 |
T85 |
2331 |
7 |
0 |
0 |
T87 |
3696 |
15 |
0 |
0 |
T103 |
34022 |
458 |
0 |
0 |
T116 |
6511 |
131 |
0 |
0 |
T119 |
10133 |
128 |
0 |
0 |
T123 |
10063 |
23 |
0 |
0 |
T124 |
5755 |
54 |
0 |
0 |
T155 |
17141 |
132 |
0 |
0 |
T156 |
14247 |
56 |
0 |
0 |
T157 |
10444 |
126 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
6782 |
0 |
0 |
T85 |
2331 |
5 |
0 |
0 |
T87 |
3696 |
9 |
0 |
0 |
T103 |
34022 |
396 |
0 |
0 |
T116 |
6511 |
130 |
0 |
0 |
T119 |
10133 |
359 |
0 |
0 |
T123 |
10063 |
149 |
0 |
0 |
T124 |
5755 |
111 |
0 |
0 |
T155 |
17141 |
109 |
0 |
0 |
T156 |
14247 |
31 |
0 |
0 |
T157 |
10444 |
10 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
7400 |
0 |
0 |
T85 |
2331 |
2 |
0 |
0 |
T87 |
3696 |
3 |
0 |
0 |
T89 |
4711 |
16 |
0 |
0 |
T103 |
34022 |
906 |
0 |
0 |
T116 |
6511 |
132 |
0 |
0 |
T119 |
10133 |
284 |
0 |
0 |
T123 |
10063 |
51 |
0 |
0 |
T155 |
17141 |
277 |
0 |
0 |
T156 |
14247 |
41 |
0 |
0 |
T157 |
10444 |
290 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
6837 |
0 |
0 |
T85 |
2331 |
6 |
0 |
0 |
T87 |
3696 |
3 |
0 |
0 |
T103 |
34022 |
764 |
0 |
0 |
T116 |
6511 |
4 |
0 |
0 |
T119 |
10133 |
248 |
0 |
0 |
T123 |
10063 |
125 |
0 |
0 |
T124 |
5755 |
55 |
0 |
0 |
T155 |
17141 |
264 |
0 |
0 |
T156 |
14247 |
58 |
0 |
0 |
T157 |
10444 |
4 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
5715 |
0 |
0 |
T85 |
2331 |
1 |
0 |
0 |
T87 |
3696 |
6 |
0 |
0 |
T103 |
34022 |
895 |
0 |
0 |
T116 |
6511 |
7 |
0 |
0 |
T119 |
10133 |
132 |
0 |
0 |
T123 |
10063 |
224 |
0 |
0 |
T124 |
5755 |
87 |
0 |
0 |
T155 |
17141 |
159 |
0 |
0 |
T156 |
14247 |
15 |
0 |
0 |
T157 |
10444 |
112 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
5946 |
0 |
0 |
T85 |
2331 |
8 |
0 |
0 |
T87 |
3696 |
8 |
0 |
0 |
T89 |
4711 |
9 |
0 |
0 |
T103 |
34022 |
566 |
0 |
0 |
T116 |
6511 |
7 |
0 |
0 |
T119 |
10133 |
121 |
0 |
0 |
T123 |
10063 |
70 |
0 |
0 |
T155 |
17141 |
353 |
0 |
0 |
T156 |
14247 |
25 |
0 |
0 |
T157 |
10444 |
121 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
7010 |
0 |
0 |
T85 |
2331 |
2 |
0 |
0 |
T87 |
3696 |
7 |
0 |
0 |
T103 |
34022 |
757 |
0 |
0 |
T116 |
6511 |
11 |
0 |
0 |
T119 |
10133 |
11 |
0 |
0 |
T123 |
10063 |
98 |
0 |
0 |
T124 |
5755 |
4 |
0 |
0 |
T155 |
17141 |
284 |
0 |
0 |
T156 |
14247 |
24 |
0 |
0 |
T157 |
10444 |
147 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3811 |
0 |
0 |
T85 |
2331 |
8 |
0 |
0 |
T87 |
3696 |
15 |
0 |
0 |
T103 |
34022 |
291 |
0 |
0 |
T116 |
6511 |
57 |
0 |
0 |
T119 |
10133 |
141 |
0 |
0 |
T123 |
10063 |
39 |
0 |
0 |
T124 |
5755 |
6 |
0 |
0 |
T155 |
17141 |
176 |
0 |
0 |
T156 |
14247 |
27 |
0 |
0 |
T157 |
10444 |
68 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3443 |
0 |
0 |
T85 |
2331 |
1 |
0 |
0 |
T87 |
3696 |
12 |
0 |
0 |
T103 |
34022 |
231 |
0 |
0 |
T116 |
6511 |
74 |
0 |
0 |
T119 |
10133 |
150 |
0 |
0 |
T123 |
10063 |
18 |
0 |
0 |
T124 |
5755 |
24 |
0 |
0 |
T155 |
17141 |
100 |
0 |
0 |
T156 |
14247 |
47 |
0 |
0 |
T157 |
10444 |
135 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3121 |
0 |
0 |
T85 |
2331 |
8 |
0 |
0 |
T87 |
3696 |
7 |
0 |
0 |
T103 |
34022 |
216 |
0 |
0 |
T116 |
6511 |
57 |
0 |
0 |
T119 |
10133 |
53 |
0 |
0 |
T123 |
10063 |
91 |
0 |
0 |
T124 |
5755 |
4 |
0 |
0 |
T155 |
17141 |
105 |
0 |
0 |
T156 |
14247 |
34 |
0 |
0 |
T157 |
10444 |
53 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3297 |
0 |
0 |
T85 |
2331 |
5 |
0 |
0 |
T87 |
3696 |
5 |
0 |
0 |
T103 |
34022 |
193 |
0 |
0 |
T116 |
6511 |
53 |
0 |
0 |
T119 |
10133 |
85 |
0 |
0 |
T123 |
10063 |
25 |
0 |
0 |
T124 |
5755 |
39 |
0 |
0 |
T155 |
17141 |
51 |
0 |
0 |
T156 |
14247 |
53 |
0 |
0 |
T157 |
10444 |
60 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3406 |
0 |
0 |
T85 |
2331 |
4 |
0 |
0 |
T87 |
3696 |
10 |
0 |
0 |
T103 |
34022 |
383 |
0 |
0 |
T116 |
6511 |
53 |
0 |
0 |
T119 |
10133 |
55 |
0 |
0 |
T123 |
10063 |
89 |
0 |
0 |
T124 |
5755 |
66 |
0 |
0 |
T155 |
17141 |
79 |
0 |
0 |
T156 |
14247 |
40 |
0 |
0 |
T157 |
10444 |
66 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3200 |
0 |
0 |
T85 |
2331 |
7 |
0 |
0 |
T87 |
3696 |
6 |
0 |
0 |
T103 |
34022 |
234 |
0 |
0 |
T116 |
6511 |
53 |
0 |
0 |
T119 |
10133 |
63 |
0 |
0 |
T123 |
10063 |
49 |
0 |
0 |
T124 |
5755 |
27 |
0 |
0 |
T155 |
17141 |
28 |
0 |
0 |
T156 |
14247 |
26 |
0 |
0 |
T157 |
10444 |
23 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3062 |
0 |
0 |
T85 |
2331 |
7 |
0 |
0 |
T87 |
3696 |
10 |
0 |
0 |
T103 |
34022 |
170 |
0 |
0 |
T116 |
6511 |
45 |
0 |
0 |
T119 |
10133 |
2 |
0 |
0 |
T123 |
10063 |
56 |
0 |
0 |
T124 |
5755 |
71 |
0 |
0 |
T155 |
17141 |
80 |
0 |
0 |
T156 |
14247 |
37 |
0 |
0 |
T157 |
10444 |
13 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3028 |
0 |
0 |
T85 |
2331 |
3 |
0 |
0 |
T87 |
3696 |
4 |
0 |
0 |
T103 |
34022 |
261 |
0 |
0 |
T116 |
6511 |
7 |
0 |
0 |
T119 |
10133 |
46 |
0 |
0 |
T123 |
10063 |
25 |
0 |
0 |
T124 |
5755 |
5 |
0 |
0 |
T155 |
17141 |
76 |
0 |
0 |
T156 |
14247 |
35 |
0 |
0 |
T157 |
10444 |
63 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3309 |
0 |
0 |
T85 |
2331 |
6 |
0 |
0 |
T87 |
3696 |
2 |
0 |
0 |
T103 |
34022 |
245 |
0 |
0 |
T116 |
6511 |
48 |
0 |
0 |
T119 |
10133 |
64 |
0 |
0 |
T123 |
10063 |
36 |
0 |
0 |
T124 |
5755 |
29 |
0 |
0 |
T155 |
17141 |
113 |
0 |
0 |
T156 |
14247 |
45 |
0 |
0 |
T157 |
10444 |
46 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3471 |
0 |
0 |
T85 |
2331 |
4 |
0 |
0 |
T87 |
3696 |
7 |
0 |
0 |
T103 |
34022 |
357 |
0 |
0 |
T116 |
6511 |
4 |
0 |
0 |
T119 |
10133 |
90 |
0 |
0 |
T123 |
10063 |
70 |
0 |
0 |
T124 |
5755 |
20 |
0 |
0 |
T155 |
17141 |
139 |
0 |
0 |
T156 |
14247 |
50 |
0 |
0 |
T157 |
10444 |
14 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3587 |
0 |
0 |
T87 |
3696 |
4 |
0 |
0 |
T89 |
4711 |
18 |
0 |
0 |
T103 |
34022 |
226 |
0 |
0 |
T116 |
6511 |
62 |
0 |
0 |
T119 |
10133 |
93 |
0 |
0 |
T123 |
10063 |
28 |
0 |
0 |
T124 |
5755 |
31 |
0 |
0 |
T155 |
17141 |
112 |
0 |
0 |
T156 |
14247 |
29 |
0 |
0 |
T157 |
10444 |
105 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3459 |
0 |
0 |
T85 |
2331 |
9 |
0 |
0 |
T87 |
3696 |
13 |
0 |
0 |
T103 |
34022 |
344 |
0 |
0 |
T116 |
6511 |
66 |
0 |
0 |
T119 |
10133 |
91 |
0 |
0 |
T123 |
10063 |
3 |
0 |
0 |
T124 |
5755 |
27 |
0 |
0 |
T155 |
17141 |
22 |
0 |
0 |
T156 |
14247 |
38 |
0 |
0 |
T157 |
10444 |
61 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3139 |
0 |
0 |
T85 |
2331 |
9 |
0 |
0 |
T87 |
3696 |
7 |
0 |
0 |
T103 |
34022 |
220 |
0 |
0 |
T116 |
6511 |
73 |
0 |
0 |
T119 |
10133 |
99 |
0 |
0 |
T123 |
10063 |
51 |
0 |
0 |
T124 |
5755 |
2 |
0 |
0 |
T155 |
17141 |
134 |
0 |
0 |
T156 |
14247 |
47 |
0 |
0 |
T157 |
10444 |
72 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3709 |
0 |
0 |
T85 |
2331 |
4 |
0 |
0 |
T87 |
3696 |
7 |
0 |
0 |
T103 |
34022 |
286 |
0 |
0 |
T116 |
6511 |
62 |
0 |
0 |
T119 |
10133 |
94 |
0 |
0 |
T123 |
10063 |
49 |
0 |
0 |
T124 |
5755 |
24 |
0 |
0 |
T155 |
17141 |
136 |
0 |
0 |
T156 |
14247 |
14 |
0 |
0 |
T157 |
10444 |
57 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3071 |
0 |
0 |
T85 |
2331 |
3 |
0 |
0 |
T87 |
3696 |
8 |
0 |
0 |
T103 |
34022 |
237 |
0 |
0 |
T116 |
6511 |
1 |
0 |
0 |
T119 |
10133 |
40 |
0 |
0 |
T123 |
10063 |
16 |
0 |
0 |
T124 |
5755 |
4 |
0 |
0 |
T155 |
17141 |
67 |
0 |
0 |
T156 |
14247 |
35 |
0 |
0 |
T157 |
10444 |
20 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3408 |
0 |
0 |
T87 |
3696 |
9 |
0 |
0 |
T89 |
4711 |
10 |
0 |
0 |
T103 |
34022 |
256 |
0 |
0 |
T116 |
6511 |
59 |
0 |
0 |
T119 |
10133 |
127 |
0 |
0 |
T123 |
10063 |
51 |
0 |
0 |
T124 |
5755 |
53 |
0 |
0 |
T155 |
17141 |
134 |
0 |
0 |
T156 |
14247 |
46 |
0 |
0 |
T157 |
10444 |
53 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3230 |
0 |
0 |
T85 |
2331 |
2 |
0 |
0 |
T87 |
3696 |
13 |
0 |
0 |
T103 |
34022 |
225 |
0 |
0 |
T116 |
6511 |
70 |
0 |
0 |
T119 |
10133 |
51 |
0 |
0 |
T123 |
10063 |
80 |
0 |
0 |
T124 |
5755 |
34 |
0 |
0 |
T155 |
17141 |
57 |
0 |
0 |
T156 |
14247 |
81 |
0 |
0 |
T157 |
10444 |
119 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3276 |
0 |
0 |
T85 |
2331 |
6 |
0 |
0 |
T87 |
3696 |
13 |
0 |
0 |
T103 |
34022 |
319 |
0 |
0 |
T116 |
6511 |
72 |
0 |
0 |
T119 |
10133 |
54 |
0 |
0 |
T123 |
10063 |
55 |
0 |
0 |
T124 |
5755 |
38 |
0 |
0 |
T155 |
17141 |
164 |
0 |
0 |
T156 |
14247 |
44 |
0 |
0 |
T157 |
10444 |
97 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3516 |
0 |
0 |
T85 |
2331 |
1 |
0 |
0 |
T87 |
3696 |
10 |
0 |
0 |
T103 |
34022 |
394 |
0 |
0 |
T116 |
6511 |
40 |
0 |
0 |
T119 |
10133 |
99 |
0 |
0 |
T123 |
10063 |
28 |
0 |
0 |
T124 |
5755 |
20 |
0 |
0 |
T155 |
17141 |
59 |
0 |
0 |
T156 |
14247 |
51 |
0 |
0 |
T157 |
10444 |
53 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3349 |
0 |
0 |
T85 |
2331 |
3 |
0 |
0 |
T87 |
3696 |
14 |
0 |
0 |
T103 |
34022 |
224 |
0 |
0 |
T116 |
6511 |
51 |
0 |
0 |
T119 |
10133 |
85 |
0 |
0 |
T123 |
10063 |
41 |
0 |
0 |
T124 |
5755 |
7 |
0 |
0 |
T155 |
17141 |
142 |
0 |
0 |
T156 |
14247 |
40 |
0 |
0 |
T157 |
10444 |
53 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3389 |
0 |
0 |
T85 |
2331 |
8 |
0 |
0 |
T87 |
3696 |
6 |
0 |
0 |
T103 |
34022 |
171 |
0 |
0 |
T116 |
6511 |
64 |
0 |
0 |
T119 |
10133 |
60 |
0 |
0 |
T123 |
10063 |
17 |
0 |
0 |
T124 |
5755 |
26 |
0 |
0 |
T155 |
17141 |
148 |
0 |
0 |
T156 |
14247 |
29 |
0 |
0 |
T157 |
10444 |
54 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3323 |
0 |
0 |
T85 |
2331 |
8 |
0 |
0 |
T87 |
3696 |
2 |
0 |
0 |
T103 |
34022 |
314 |
0 |
0 |
T116 |
6511 |
47 |
0 |
0 |
T119 |
10133 |
49 |
0 |
0 |
T123 |
10063 |
30 |
0 |
0 |
T124 |
5755 |
41 |
0 |
0 |
T155 |
17141 |
18 |
0 |
0 |
T156 |
14247 |
29 |
0 |
0 |
T157 |
10444 |
113 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3480 |
0 |
0 |
T85 |
2331 |
2 |
0 |
0 |
T87 |
3696 |
5 |
0 |
0 |
T103 |
34022 |
231 |
0 |
0 |
T116 |
6511 |
45 |
0 |
0 |
T119 |
10133 |
58 |
0 |
0 |
T123 |
10063 |
66 |
0 |
0 |
T124 |
5755 |
71 |
0 |
0 |
T155 |
17141 |
116 |
0 |
0 |
T156 |
14247 |
49 |
0 |
0 |
T157 |
10444 |
66 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3201 |
0 |
0 |
T85 |
2331 |
1 |
0 |
0 |
T87 |
3696 |
5 |
0 |
0 |
T103 |
34022 |
255 |
0 |
0 |
T116 |
6511 |
60 |
0 |
0 |
T119 |
10133 |
2 |
0 |
0 |
T123 |
10063 |
29 |
0 |
0 |
T124 |
5755 |
46 |
0 |
0 |
T155 |
17141 |
116 |
0 |
0 |
T156 |
14247 |
57 |
0 |
0 |
T157 |
10444 |
22 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1435 |
0 |
0 |
T85 |
2331 |
6 |
0 |
0 |
T87 |
3696 |
14 |
0 |
0 |
T103 |
34022 |
23 |
0 |
0 |
T116 |
6511 |
14 |
0 |
0 |
T119 |
10133 |
6 |
0 |
0 |
T123 |
10063 |
4 |
0 |
0 |
T124 |
5755 |
9 |
0 |
0 |
T155 |
17141 |
38 |
0 |
0 |
T156 |
14247 |
29 |
0 |
0 |
T157 |
10444 |
27 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1394 |
0 |
0 |
T87 |
3696 |
1 |
0 |
0 |
T89 |
4711 |
11 |
0 |
0 |
T103 |
34022 |
55 |
0 |
0 |
T116 |
6511 |
21 |
0 |
0 |
T119 |
10133 |
25 |
0 |
0 |
T123 |
10063 |
23 |
0 |
0 |
T124 |
5755 |
10 |
0 |
0 |
T155 |
17141 |
36 |
0 |
0 |
T156 |
14247 |
27 |
0 |
0 |
T157 |
10444 |
24 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1497 |
0 |
0 |
T85 |
2331 |
2 |
0 |
0 |
T87 |
3696 |
6 |
0 |
0 |
T103 |
34022 |
39 |
0 |
0 |
T116 |
6511 |
17 |
0 |
0 |
T119 |
10133 |
32 |
0 |
0 |
T123 |
10063 |
10 |
0 |
0 |
T124 |
5755 |
6 |
0 |
0 |
T155 |
17141 |
44 |
0 |
0 |
T156 |
14247 |
62 |
0 |
0 |
T157 |
10444 |
31 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1483 |
0 |
0 |
T85 |
2331 |
5 |
0 |
0 |
T87 |
3696 |
1 |
0 |
0 |
T103 |
34022 |
46 |
0 |
0 |
T116 |
6511 |
10 |
0 |
0 |
T119 |
10133 |
11 |
0 |
0 |
T123 |
10063 |
12 |
0 |
0 |
T124 |
5755 |
2 |
0 |
0 |
T155 |
17141 |
16 |
0 |
0 |
T156 |
14247 |
61 |
0 |
0 |
T157 |
10444 |
16 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1769 |
0 |
0 |
T85 |
2331 |
9 |
0 |
0 |
T87 |
3696 |
12 |
0 |
0 |
T103 |
34022 |
80 |
0 |
0 |
T116 |
6511 |
10 |
0 |
0 |
T119 |
10133 |
25 |
0 |
0 |
T123 |
10063 |
15 |
0 |
0 |
T124 |
5755 |
15 |
0 |
0 |
T155 |
17141 |
47 |
0 |
0 |
T156 |
14247 |
45 |
0 |
0 |
T157 |
10444 |
38 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
3518 |
0 |
0 |
T13 |
569158 |
64 |
0 |
0 |
T15 |
0 |
50 |
0 |
0 |
T16 |
0 |
13 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T23 |
285389 |
0 |
0 |
0 |
T24 |
2103 |
0 |
0 |
0 |
T25 |
614142 |
0 |
0 |
0 |
T26 |
781 |
0 |
0 |
0 |
T27 |
302371 |
0 |
0 |
0 |
T28 |
1875 |
0 |
0 |
0 |
T29 |
1067 |
0 |
0 |
0 |
T30 |
271942 |
0 |
0 |
0 |
T35 |
2525 |
0 |
0 |
0 |
T158 |
0 |
59 |
0 |
0 |
T159 |
0 |
70 |
0 |
0 |
T160 |
0 |
14 |
0 |
0 |
T161 |
0 |
13 |
0 |
0 |
T162 |
0 |
36 |
0 |
0 |
T163 |
0 |
14 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1462 |
0 |
0 |
T85 |
2331 |
1 |
0 |
0 |
T87 |
3696 |
4 |
0 |
0 |
T103 |
34022 |
63 |
0 |
0 |
T116 |
6511 |
10 |
0 |
0 |
T119 |
10133 |
23 |
0 |
0 |
T123 |
10063 |
27 |
0 |
0 |
T124 |
5755 |
2 |
0 |
0 |
T155 |
17141 |
21 |
0 |
0 |
T156 |
14247 |
44 |
0 |
0 |
T157 |
10444 |
14 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1369 |
0 |
0 |
T85 |
2331 |
4 |
0 |
0 |
T87 |
3696 |
12 |
0 |
0 |
T103 |
34022 |
71 |
0 |
0 |
T116 |
6511 |
6 |
0 |
0 |
T119 |
10133 |
18 |
0 |
0 |
T123 |
10063 |
7 |
0 |
0 |
T124 |
5755 |
13 |
0 |
0 |
T155 |
17141 |
34 |
0 |
0 |
T156 |
14247 |
26 |
0 |
0 |
T157 |
10444 |
35 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1210 |
0 |
0 |
T85 |
2331 |
1 |
0 |
0 |
T87 |
3696 |
10 |
0 |
0 |
T89 |
4711 |
13 |
0 |
0 |
T103 |
34022 |
45 |
0 |
0 |
T116 |
6511 |
9 |
0 |
0 |
T119 |
10133 |
12 |
0 |
0 |
T123 |
10063 |
4 |
0 |
0 |
T155 |
17141 |
29 |
0 |
0 |
T156 |
14247 |
28 |
0 |
0 |
T157 |
10444 |
14 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1250 |
0 |
0 |
T85 |
2331 |
5 |
0 |
0 |
T87 |
3696 |
10 |
0 |
0 |
T103 |
34022 |
43 |
0 |
0 |
T116 |
6511 |
6 |
0 |
0 |
T119 |
10133 |
16 |
0 |
0 |
T123 |
10063 |
9 |
0 |
0 |
T124 |
5755 |
10 |
0 |
0 |
T155 |
17141 |
26 |
0 |
0 |
T156 |
14247 |
14 |
0 |
0 |
T157 |
10444 |
7 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1220 |
0 |
0 |
T85 |
2331 |
3 |
0 |
0 |
T87 |
3696 |
13 |
0 |
0 |
T103 |
34022 |
42 |
0 |
0 |
T116 |
6511 |
3 |
0 |
0 |
T119 |
10133 |
5 |
0 |
0 |
T123 |
10063 |
5 |
0 |
0 |
T124 |
5755 |
5 |
0 |
0 |
T155 |
17141 |
23 |
0 |
0 |
T156 |
14247 |
30 |
0 |
0 |
T157 |
10444 |
11 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1135 |
0 |
0 |
T85 |
2331 |
4 |
0 |
0 |
T87 |
3696 |
12 |
0 |
0 |
T89 |
4711 |
18 |
0 |
0 |
T103 |
34022 |
38 |
0 |
0 |
T116 |
6511 |
9 |
0 |
0 |
T119 |
10133 |
5 |
0 |
0 |
T124 |
5755 |
7 |
0 |
0 |
T155 |
17141 |
27 |
0 |
0 |
T156 |
14247 |
57 |
0 |
0 |
T157 |
10444 |
20 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1742 |
0 |
0 |
T85 |
2331 |
3 |
0 |
0 |
T87 |
3696 |
10 |
0 |
0 |
T103 |
34022 |
79 |
0 |
0 |
T116 |
6511 |
11 |
0 |
0 |
T119 |
10133 |
35 |
0 |
0 |
T123 |
10063 |
18 |
0 |
0 |
T124 |
5755 |
21 |
0 |
0 |
T155 |
17141 |
31 |
0 |
0 |
T156 |
14247 |
44 |
0 |
0 |
T157 |
10444 |
34 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1241 |
0 |
0 |
T87 |
3696 |
2 |
0 |
0 |
T89 |
4711 |
20 |
0 |
0 |
T103 |
34022 |
26 |
0 |
0 |
T116 |
6511 |
6 |
0 |
0 |
T119 |
10133 |
7 |
0 |
0 |
T123 |
10063 |
9 |
0 |
0 |
T124 |
5755 |
2 |
0 |
0 |
T155 |
17141 |
6 |
0 |
0 |
T156 |
14247 |
56 |
0 |
0 |
T157 |
10444 |
13 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1872 |
0 |
0 |
T85 |
2331 |
2 |
0 |
0 |
T87 |
3696 |
1 |
0 |
0 |
T103 |
34022 |
130 |
0 |
0 |
T116 |
6511 |
4 |
0 |
0 |
T119 |
10133 |
26 |
0 |
0 |
T123 |
10063 |
13 |
0 |
0 |
T124 |
5755 |
1 |
0 |
0 |
T155 |
17141 |
47 |
0 |
0 |
T156 |
14247 |
23 |
0 |
0 |
T157 |
10444 |
9 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1414 |
0 |
0 |
T85 |
2331 |
4 |
0 |
0 |
T89 |
4711 |
6 |
0 |
0 |
T103 |
34022 |
67 |
0 |
0 |
T116 |
6511 |
16 |
0 |
0 |
T119 |
10133 |
24 |
0 |
0 |
T123 |
10063 |
2 |
0 |
0 |
T155 |
17141 |
10 |
0 |
0 |
T156 |
14247 |
46 |
0 |
0 |
T157 |
10444 |
19 |
0 |
0 |
T164 |
32501 |
34 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1222 |
0 |
0 |
T87 |
3696 |
3 |
0 |
0 |
T89 |
4711 |
3 |
0 |
0 |
T103 |
34022 |
35 |
0 |
0 |
T116 |
6511 |
8 |
0 |
0 |
T119 |
10133 |
10 |
0 |
0 |
T123 |
10063 |
4 |
0 |
0 |
T124 |
5755 |
3 |
0 |
0 |
T155 |
17141 |
21 |
0 |
0 |
T156 |
14247 |
30 |
0 |
0 |
T157 |
10444 |
18 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1259 |
0 |
0 |
T85 |
2331 |
2 |
0 |
0 |
T87 |
3696 |
14 |
0 |
0 |
T103 |
34022 |
42 |
0 |
0 |
T116 |
6511 |
14 |
0 |
0 |
T119 |
10133 |
18 |
0 |
0 |
T123 |
10063 |
14 |
0 |
0 |
T124 |
5755 |
7 |
0 |
0 |
T155 |
17141 |
18 |
0 |
0 |
T156 |
14247 |
33 |
0 |
0 |
T157 |
10444 |
25 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1277 |
0 |
0 |
T85 |
2331 |
7 |
0 |
0 |
T87 |
3696 |
18 |
0 |
0 |
T89 |
4711 |
16 |
0 |
0 |
T103 |
34022 |
35 |
0 |
0 |
T116 |
6511 |
19 |
0 |
0 |
T119 |
10133 |
16 |
0 |
0 |
T123 |
10063 |
7 |
0 |
0 |
T155 |
17141 |
10 |
0 |
0 |
T156 |
14247 |
46 |
0 |
0 |
T157 |
10444 |
11 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1296 |
0 |
0 |
T87 |
3696 |
12 |
0 |
0 |
T89 |
4711 |
13 |
0 |
0 |
T103 |
34022 |
28 |
0 |
0 |
T116 |
6511 |
12 |
0 |
0 |
T119 |
10133 |
6 |
0 |
0 |
T123 |
10063 |
17 |
0 |
0 |
T124 |
5755 |
2 |
0 |
0 |
T155 |
17141 |
29 |
0 |
0 |
T156 |
14247 |
67 |
0 |
0 |
T157 |
10444 |
9 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1233 |
0 |
0 |
T85 |
2331 |
4 |
0 |
0 |
T87 |
3696 |
3 |
0 |
0 |
T103 |
34022 |
32 |
0 |
0 |
T116 |
6511 |
13 |
0 |
0 |
T119 |
10133 |
15 |
0 |
0 |
T123 |
10063 |
7 |
0 |
0 |
T124 |
5755 |
6 |
0 |
0 |
T155 |
17141 |
13 |
0 |
0 |
T156 |
14247 |
42 |
0 |
0 |
T157 |
10444 |
11 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
473445271 |
1249 |
0 |
0 |
T85 |
2331 |
1 |
0 |
0 |
T87 |
3696 |
4 |
0 |
0 |
T103 |
34022 |
40 |
0 |
0 |
T116 |
6511 |
4 |
0 |
0 |
T119 |
10133 |
4 |
0 |
0 |
T123 |
10063 |
3 |
0 |
0 |
T124 |
5755 |
8 |
0 |
0 |
T155 |
17141 |
23 |
0 |
0 |
T156 |
14247 |
50 |
0 |
0 |
T157 |
10444 |
14 |
0 |
0 |