Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4068323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4559151

1

T1

4183

T2

14073

T3

6787

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4883383	1			T1	4601		T2	26171		T3	3169
values[0x0]	1869789	1			T1	2059		T2	442		T3	3344
values[0x1]	1874302	1			T1	2014		T2	454		T3	3256

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2886040	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5741434

1

T1

5560

T2

16692

T3

7621

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32810	1			T1	399		T2	91		T4	3
valid_sources[0x01]	30375	1			T2	84		T3	19		T4	7
valid_sources[0x02]	31447	1			T1	2		T2	85		T3	34
valid_sources[0x03]	33281	1			T1	1		T2	115		T3	13
valid_sources[0x04]	30334	1			T2	115		T3	68		T4	13
valid_sources[0x05]	30638	1			T2	109		T3	17		T4	4
valid_sources[0x06]	31246	1			T2	148		T3	7		T4	9
valid_sources[0x07]	34042	1			T2	103		T3	21		T4	3
valid_sources[0x08]	29315	1			T1	2		T2	83		T3	43
valid_sources[0x09]	38150	1			T2	111		T3	9		T4	7
valid_sources[0x0a]	37689	1			T2	104		T3	24		T4	7
valid_sources[0x0b]	33217	1			T1	274		T2	114		T3	75
valid_sources[0x0c]	30196	1			T1	400		T2	115		T3	28
valid_sources[0x0d]	30026	1			T1	62		T2	92		T3	6
valid_sources[0x0e]	31900	1			T1	292		T2	101		T3	31
valid_sources[0x0f]	31958	1			T2	94		T3	23		T4	5
valid_sources[0x10]	33364	1			T2	127		T3	127		T4	3
valid_sources[0x11]	32634	1			T1	3		T2	122		T3	98
valid_sources[0x12]	32291	1			T1	69		T2	71		T3	80
valid_sources[0x13]	35257	1			T2	118		T3	80		T4	3
valid_sources[0x14]	31903	1			T1	1		T2	100		T3	12
valid_sources[0x15]	31803	1			T2	94		T3	29		T4	5
valid_sources[0x16]	30076	1			T2	95		T3	37		T4	10
valid_sources[0x17]	30528	1			T1	2		T2	120		T3	48
valid_sources[0x18]	30837	1			T2	124		T3	52		T4	6
valid_sources[0x19]	29337	1			T1	19		T2	102		T4	11
valid_sources[0x1a]	36894	1			T1	46		T2	73		T3	26
valid_sources[0x1b]	33122	1			T2	150		T3	6		T4	14
valid_sources[0x1c]	35719	1			T1	56		T2	80		T3	31
valid_sources[0x1d]	34401	1			T2	118		T3	10		T4	1
valid_sources[0x1e]	29646	1			T2	85		T3	52		T4	3
valid_sources[0x1f]	33957	1			T1	3		T2	118		T3	7
valid_sources[0x20]	29703	1			T2	91		T3	4		T4	2
valid_sources[0x21]	33745	1			T2	117		T3	88		T4	5
valid_sources[0x22]	31562	1			T2	212		T3	39		T4	10
valid_sources[0x23]	33200	1			T1	854		T2	133		T3	101
valid_sources[0x24]	33981	1			T2	92		T3	29		T4	10
valid_sources[0x25]	32098	1			T1	1		T2	158		T3	85
valid_sources[0x26]	31257	1			T2	80		T3	34		T4	6
valid_sources[0x27]	34083	1			T2	116		T4	18		T5	4
valid_sources[0x28]	31486	1			T1	1		T2	104		T3	13
valid_sources[0x29]	39013	1			T1	103		T2	106		T3	2
valid_sources[0x2a]	33406	1			T1	2		T2	123		T3	62
valid_sources[0x2b]	31346	1			T2	100		T3	55		T4	4
valid_sources[0x2c]	36483	1			T2	131		T4	6		T5	2
valid_sources[0x2d]	32315	1			T1	3		T2	100		T3	4
valid_sources[0x2e]	30811	1			T2	108		T3	38		T4	7
valid_sources[0x2f]	32664	1			T1	1		T2	82		T3	54
valid_sources[0x30]	32279	1			T1	204		T2	139		T3	24
valid_sources[0x31]	31270	1			T2	99		T3	1		T4	15
valid_sources[0x32]	35096	1			T2	88		T3	71		T4	6
valid_sources[0x33]	32492	1			T2	119		T3	32		T4	1
valid_sources[0x34]	31344	1			T1	18		T2	112		T3	25
valid_sources[0x35]	29048	1			T2	84		T4	5		T5	8
valid_sources[0x36]	32010	1			T2	123		T4	4		T5	4
valid_sources[0x37]	35367	1			T1	1		T2	71		T3	119
valid_sources[0x38]	31931	1			T2	96		T3	9		T4	5
valid_sources[0x39]	30165	1			T1	2		T2	110		T3	35
valid_sources[0x3a]	32309	1			T1	4		T2	99		T3	43
valid_sources[0x3b]	31382	1			T2	92		T4	4		T5	1
valid_sources[0x3c]	31235	1			T2	77		T3	67		T4	5
valid_sources[0x3d]	49065	1			T1	28		T2	80		T3	157
valid_sources[0x3e]	32863	1			T2	85		T3	52		T4	8
valid_sources[0x3f]	32198	1			T1	185		T2	131		T3	59
valid_sources[0x40]	31342	1			T2	90		T3	11		T4	9
valid_sources[0x41]	33796	1			T2	117		T3	16		T4	5
valid_sources[0x42]	33785	1			T1	65		T2	84		T3	22
valid_sources[0x43]	30905	1			T2	135		T3	28		T4	5
valid_sources[0x44]	32816	1			T1	4		T2	88		T3	11
valid_sources[0x45]	32656	1			T2	80		T3	9		T4	5
valid_sources[0x46]	31275	1			T2	117		T3	101		T4	7
valid_sources[0x47]	32750	1			T2	122		T4	6		T6	3
valid_sources[0x48]	34421	1			T1	1		T2	120		T3	59
valid_sources[0x49]	31500	1			T1	412		T2	79		T3	23
valid_sources[0x4a]	34700	1			T1	46		T2	124		T3	19
valid_sources[0x4b]	30636	1			T1	124		T2	125		T3	46
valid_sources[0x4c]	35627	1			T2	92		T3	18		T4	6
valid_sources[0x4d]	35620	1			T1	87		T2	125		T3	1
valid_sources[0x4e]	32304	1			T2	122		T3	19		T4	6
valid_sources[0x4f]	31297	1			T2	87		T3	11		T4	8
valid_sources[0x50]	31025	1			T2	109		T3	24		T4	8
valid_sources[0x51]	30451	1			T1	27		T2	127		T3	22
valid_sources[0x52]	36004	1			T2	86		T3	23		T4	8
valid_sources[0x53]	33050	1			T2	107		T3	10		T4	5
valid_sources[0x54]	32054	1			T2	81		T3	13		T4	9
valid_sources[0x55]	32160	1			T2	119		T3	92		T4	6
valid_sources[0x56]	33352	1			T1	159		T2	137		T3	4
valid_sources[0x57]	34884	1			T2	83		T3	18		T4	6
valid_sources[0x58]	38271	1			T1	2		T2	127		T3	2
valid_sources[0x59]	31537	1			T2	120		T3	72		T4	4
valid_sources[0x5a]	31131	1			T1	4		T2	67		T3	13
valid_sources[0x5b]	30434	1			T2	95		T4	7		T5	5
valid_sources[0x5c]	33342	1			T1	1		T2	105		T3	2
valid_sources[0x5d]	29863	1			T2	128		T3	44		T4	7
valid_sources[0x5e]	81401	1			T2	113		T3	12		T4	7
valid_sources[0x5f]	31836	1			T2	117		T3	10		T4	7
valid_sources[0x60]	31686	1			T1	2		T2	78		T3	99
valid_sources[0x61]	34794	1			T1	94		T2	93		T3	1
valid_sources[0x62]	31514	1			T2	69		T4	14		T5	1
valid_sources[0x63]	35861	1			T2	100		T3	16		T4	9
valid_sources[0x64]	33314	1			T2	99		T3	59		T4	6
valid_sources[0x65]	39490	1			T1	2		T2	100		T3	57
valid_sources[0x66]	32913	1			T1	370		T2	101		T3	12
valid_sources[0x67]	30029	1			T1	1		T2	98		T3	41
valid_sources[0x68]	37290	1			T2	144		T3	27		T4	7
valid_sources[0x69]	33679	1			T2	112		T3	84		T4	2
valid_sources[0x6a]	34447	1			T1	5		T2	118		T3	53
valid_sources[0x6b]	33818	1			T2	99		T3	79		T4	6
valid_sources[0x6c]	32928	1			T2	99		T3	117		T4	4
valid_sources[0x6d]	32212	1			T1	2		T2	107		T3	35
valid_sources[0x6e]	34659	1			T2	108		T4	3		T5	3
valid_sources[0x6f]	40448	1			T2	117		T3	1		T4	8
valid_sources[0x70]	40032	1			T2	106		T3	12		T4	12
valid_sources[0x71]	32515	1			T2	101		T3	7		T4	8
valid_sources[0x72]	32551	1			T1	1		T2	170		T3	24
valid_sources[0x73]	30980	1			T2	96		T3	140		T4	11
valid_sources[0x74]	30429	1			T1	5		T2	94		T3	239
valid_sources[0x75]	33508	1			T1	64		T2	89		T3	42
valid_sources[0x76]	32247	1			T2	108		T3	19		T4	11
valid_sources[0x77]	32188	1			T2	95		T3	59		T4	6
valid_sources[0x78]	30466	1			T2	105		T3	2		T4	9
valid_sources[0x79]	31091	1			T2	96		T3	38		T4	13
valid_sources[0x7a]	31185	1			T2	106		T3	35		T4	6
valid_sources[0x7b]	38353	1			T2	85		T3	73		T4	10
valid_sources[0x7c]	48033	1			T2	96		T3	56		T4	5
valid_sources[0x7d]	30441	1			T2	114		T3	17		T4	8
valid_sources[0x7e]	31683	1			T2	123		T3	11		T4	4
valid_sources[0x7f]	31387	1			T1	6		T2	116		T3	15
valid_sources[0x80]	31805	1			T2	98		T3	53		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1183280

1

T1

1100

T2

13184

T3

849

values[0x0]

all_enables

biggest_size

1699529

1

T1

1602

T2

441

T3

3056

values[0x1]

all_enables

biggest_size

1676342

1

T1

1481

T2

448

T3

2882