Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4086241

1

T1

4491

T2

12994

T3

2982

full_word

4558032

1

T1

4183

T2

14073

T3

6787

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8643913	1			T1	8674		T2	27067		T3	9769
auto[TlIntgErrCmd]	127	1			T88	2		T89	3		T93	5
auto[TlIntgErrData]	136	1			T88	4		T89	3		T93	3
auto[TlIntgErrBoth]	97	1			T88	4		T89	4		T93	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4884408

1

T1

4601

T2

26171

T3

3169

auto[1]

3759865

1

T1

4073

T2

896

T3

6600

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3700944	1			T1	3501		T2	12987		T3	2320
auto[TlIntgErrNone]	partial	auto[1]	384962	1			T1	990		T2	7		T3	662
auto[TlIntgErrNone]	full_word	auto[0]	1183303	1			T1	1100		T2	13184		T3	849
auto[TlIntgErrNone]	full_word	auto[1]	3374704	1			T1	3083		T2	889		T3	5938
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T88	1		T89	2		T93	2
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T88	1		T89	1		T93	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T166	1		T169	1		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T169	1		T171	1		T172	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T88	2		T89	1		T93	1
auto[TlIntgErrData]	partial	auto[1]	57	1			T88	2		T89	2		T93	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T144	1		T145	1		T171	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T166	1		T145	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T88	1		T89	1		T93	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T88	3		T89	3		T93	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T173	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T174	1		-	-		-	-