Group : spi_device_env_pkg::busy_blocks_command_cg
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Group : spi_device_env_pkg::busy_blocks_command_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
spi_device_env_pkg.en4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.ex4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.upload_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wrdi_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wren_block_cmd_cg 100.00 1 100 1 64 64




Group Instance : spi_device_env_pkg.en4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.en4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.en4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.ex4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.upload_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.upload_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.upload_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wrdi_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wren_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wren_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wren_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 27 1 T26 1 T44 1 T85 1
allowed 1541 1 T3 4 T4 1 T11 3


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 24 1 T85 1 T175 1 T176 2
allowed 1544 1 T3 7 T4 3 T11 5


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 185 1 T44 6 T84 2 T85 8
allowed 4844 1 T3 12 T11 34 T12 120


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 17 1 T82 1 T177 3 T178 1
allowed 1548 1 T3 4 T4 4 T11 13


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 18 1 T179 1 T178 1 T180 2
allowed 1532 1 T3 5 T4 2 T11 4

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