Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476603646	2931783	0	0
DepthKnown_A	476603646	476471934	0	0
RvalidKnown_A	476603646	476471934	0	0
WreadyKnown_A	476603646	476471934	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	2931783	0	0
T2	694174	1663	0	0
T3	181068	7484	0	0
T4	56645	2495	0	0
T5	3036	1663	0	0
T6	7935	0	0	0
T7	27998	832	0	0
T8	15332	1663	0	0
T9	18518	1665	0	0
T10	199171	1663	0	0
T11	154274	10812	0	0
T12	0	40754	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476603646	3197428	0	0
DepthKnown_A	476603646	476471934	0	0
RvalidKnown_A	476603646	476471934	0	0
WreadyKnown_A	476603646	476471934	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	3197428	0	0
T2	694174	832	0	0
T3	181068	4160	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	0	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	834	0	0
T10	199171	832	0	0
T11	154274	7488	0	0
T12	0	29120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476603646	201148	0	0
DepthKnown_A	476603646	476471934	0	0
RvalidKnown_A	476603646	476471934	0	0
WreadyKnown_A	476603646	476471934	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	201148	0	0
T1	277761	906	0	0
T2	694174	0	0	0
T3	181068	610	0	0
T4	56645	0	0	0
T5	3036	0	0	0
T6	7935	16	0	0
T7	27998	0	0	0
T8	15332	0	0	0
T9	18518	0	0	0
T10	199171	0	0	0
T11	0	1031	0	0
T12	0	2858	0	0
T25	0	486	0	0
T26	0	192	0	0
T28	0	128	0	0
T32	0	1	0	0
T39	0	184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476603646	457170	0	0
DepthKnown_A	476603646	476471934	0	0
RvalidKnown_A	476603646	476471934	0	0
WreadyKnown_A	476603646	476471934	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	457170	0	0
T1	277761	906	0	0
T2	694174	0	0	0
T3	181068	610	0	0
T4	56645	0	0	0
T5	3036	0	0	0
T6	7935	16	0	0
T7	27998	0	0	0
T8	15332	0	0	0
T9	18518	0	0	0
T10	199171	0	0	0
T11	0	1031	0	0
T12	0	2858	0	0
T25	0	2322	0	0
T26	0	854	0	0
T28	0	128	0	0
T32	0	1	0	0
T39	0	184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476603646	6935282	0	0
DepthKnown_A	476603646	476471934	0	0
RvalidKnown_A	476603646	476471934	0	0
WreadyKnown_A	476603646	476471934	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	6935282	0	0
T1	277761	7796	0	0
T2	694174	26242	0	0
T3	181068	5057	0	0
T4	56645	227	0	0
T5	3036	65	0	0
T6	7935	1894	0	0
T7	27998	788	0	0
T8	15332	68	0	0
T9	18518	353	0	0
T10	199171	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476603646	14321394	0	0
DepthKnown_A	476603646	476471934	0	0
RvalidKnown_A	476603646	476471934	0	0
WreadyKnown_A	476603646	476471934	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	14321394	0	0
T1	277761	7768	0	0
T2	694174	113715	0	0
T3	181068	4999	0	0
T4	56645	227	0	0
T5	3036	65	0	0
T6	7935	1894	0	0
T7	27998	787	0	0
T8	15332	68	0	0
T9	18518	1027	0	0
T10	199171	138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476603646	476471934	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0