Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	780621928	625820609	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	780621928	3822659	0	0
GntImpliesValid_A	780621928	3822659	0	0
GrantKnown_A	780621928	625820609	0	0
IdxKnown_A	780621928	625820609	0	0
IndexIsCorrect_A	780621928	3822659	0	0
LockArbDecision_A	780621928	0	0	0
NoReadyValidNoGrant_A	780621928	0	0	0
ReadyAndValidImplyGrant_A	780621928	3822659	0	0
ReqAndReadyImplyGrant_A	780621928	3822659	0	0
ReqImpliesValid_A	780621928	3822659	0	0
ReqStaysHighUntilGranted0_M	780621928	0	0	0
RoundRobin_A	780621928	6	0	975
ValidKnown_A	780621928	625820609	0	0
gen_data_port_assertion.DataFlow_A	780621928	3822659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	625820609	0	0
T1	492185	485731	0	0
T2	924350	809184	0	0
T3	1166086	669910	0	0
T4	217993	136626	0	0
T5	3132	3008	0	0
T6	10175	8976	0	0
T7	67908	47660	0	0
T8	23756	19467	0	0
T9	48114	33246	0	0
T10	248635	223587	0	0
T11	495587	488808	0	0
T12	0	366480	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	3822659	0	0
T1	492185	8202	0	0
T2	809262	832	0	0
T3	1166086	10999	0	0
T4	217993	1664	0	0
T5	3132	832	0	0
T6	10175	112	0	0
T7	67908	832	0	0
T8	23756	832	0	0
T9	48114	832	0	0
T10	248635	832	0	0
T11	495587	7129	0	0
T12	0	20370	0	0
T25	0	2980	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T32	0	10	0	0
T33	0	7266	0	0
T38	0	3301	0	0
T39	0	1181	0	0
T44	0	271	0	0
T47	0	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	3822659	0	0
T1	492185	8202	0	0
T2	809262	832	0	0
T3	1166086	10999	0	0
T4	217993	1664	0	0
T5	3132	832	0	0
T6	10175	112	0	0
T7	67908	832	0	0
T8	23756	832	0	0
T9	48114	832	0	0
T10	248635	832	0	0
T11	495587	7129	0	0
T12	0	20370	0	0
T25	0	2980	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T32	0	10	0	0
T33	0	7266	0	0
T38	0	3301	0	0
T39	0	1181	0	0
T44	0	271	0	0
T47	0	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	625820609	0	0
T1	492185	485731	0	0
T2	924350	809184	0	0
T3	1166086	669910	0	0
T4	217993	136626	0	0
T5	3132	3008	0	0
T6	10175	8976	0	0
T7	67908	47660	0	0
T8	23756	19467	0	0
T9	48114	33246	0	0
T10	248635	223587	0	0
T11	495587	488808	0	0
T12	0	366480	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	625820609	0	0
T1	492185	485731	0	0
T2	924350	809184	0	0
T3	1166086	669910	0	0
T4	217993	136626	0	0
T5	3132	3008	0	0
T6	10175	8976	0	0
T7	67908	47660	0	0
T8	23756	19467	0	0
T9	48114	33246	0	0
T10	248635	223587	0	0
T11	495587	488808	0	0
T12	0	366480	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	3822659	0	0
T1	492185	8202	0	0
T2	809262	832	0	0
T3	1166086	10999	0	0
T4	217993	1664	0	0
T5	3132	832	0	0
T6	10175	112	0	0
T7	67908	832	0	0
T8	23756	832	0	0
T9	48114	832	0	0
T10	248635	832	0	0
T11	495587	7129	0	0
T12	0	20370	0	0
T25	0	2980	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T32	0	10	0	0
T33	0	7266	0	0
T38	0	3301	0	0
T39	0	1181	0	0
T44	0	271	0	0
T47	0	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	3822659	0	0
T1	492185	8202	0	0
T2	809262	832	0	0
T3	1166086	10999	0	0
T4	217993	1664	0	0
T5	3132	832	0	0
T6	10175	112	0	0
T7	67908	832	0	0
T8	23756	832	0	0
T9	48114	832	0	0
T10	248635	832	0	0
T11	495587	7129	0	0
T12	0	20370	0	0
T25	0	2980	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T32	0	10	0	0
T33	0	7266	0	0
T38	0	3301	0	0
T39	0	1181	0	0
T44	0	271	0	0
T47	0	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	3822659	0	0
T1	492185	8202	0	0
T2	809262	832	0	0
T3	1166086	10999	0	0
T4	217993	1664	0	0
T5	3132	832	0	0
T6	10175	112	0	0
T7	67908	832	0	0
T8	23756	832	0	0
T9	48114	832	0	0
T10	248635	832	0	0
T11	495587	7129	0	0
T12	0	20370	0	0
T25	0	2980	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T32	0	10	0	0
T33	0	7266	0	0
T38	0	3301	0	0
T39	0	1181	0	0
T44	0	271	0	0
T47	0	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	3822659	0	0
T1	492185	8202	0	0
T2	809262	832	0	0
T3	1166086	10999	0	0
T4	217993	1664	0	0
T5	3132	832	0	0
T6	10175	112	0	0
T7	67908	832	0	0
T8	23756	832	0	0
T9	48114	832	0	0
T10	248635	832	0	0
T11	495587	7129	0	0
T12	0	20370	0	0
T25	0	2980	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T32	0	10	0	0
T33	0	7266	0	0
T38	0	3301	0	0
T39	0	1181	0	0
T44	0	271	0	0
T47	0	120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	6	0	975
T12	945126	1	0	1
T15	0	1	0	0
T22	389891	0	0	1
T23	33963	0	0	1
T24	3139	0	0	1
T25	579077	0	0	1
T26	807657	0	0	1
T27	980	0	0	1
T28	98175	0	0	1
T29	36481	0	0	1
T30	1156	0	0	1
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	625820609	0	0
T1	492185	485731	0	0
T2	924350	809184	0	0
T3	1166086	669910	0	0
T4	217993	136626	0	0
T5	3132	3008	0	0
T6	10175	8976	0	0
T7	67908	47660	0	0
T8	23756	19467	0	0
T9	48114	33246	0	0
T10	248635	223587	0	0
T11	495587	488808	0	0
T12	0	366480	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780621928	3822659	0	0
T1	492185	8202	0	0
T2	809262	832	0	0
T3	1166086	10999	0	0
T4	217993	1664	0	0
T5	3132	832	0	0
T6	10175	112	0	0
T7	67908	832	0	0
T8	23756	832	0	0
T9	48114	832	0	0
T10	248635	832	0	0
T11	495587	7129	0	0
T12	0	20370	0	0
T25	0	2980	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T32	0	10	0	0
T33	0	7266	0	0
T38	0	3301	0	0
T39	0	1181	0	0
T44	0	271	0	0
T47	0	120	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153278707	29262376	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	153278707	681344	0	0
GntImpliesValid_A	153278707	681344	0	0
GrantKnown_A	153278707	29262376	0	0
IdxKnown_A	153278707	29262376	0	0
IndexIsCorrect_A	153278707	681344	0	0
LockArbDecision_A	153278707	0	0	0
NoReadyValidNoGrant_A	153278707	0	0	0
ReadyAndValidImplyGrant_A	153278707	681344	0	0
ReqAndReadyImplyGrant_A	153278707	681344	0	0
ReqImpliesValid_A	153278707	681344	0	0
ReqStaysHighUntilGranted0_M	153278707	0	0	0
RoundRobin_A	153278707	0	0	0
ValidKnown_A	153278707	29262376	0	0
gen_data_port_assertion.DataFlow_A	153278707	681344	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	29262376	0	0
T1	214424	208056	0	0
T2	115088	0	0	0
T3	492509	197384	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	1120	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	68952	0	0
T12	0	204288	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	681344	0	0
T1	214424	5486	0	0
T2	115088	0	0	0
T3	492509	2374	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	80	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	2703	0	0
T12	0	8424	0	0
T25	0	1941	0	0
T32	0	10	0	0
T33	0	4132	0	0
T39	0	1181	0	0
T47	0	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	681344	0	0
T1	214424	5486	0	0
T2	115088	0	0	0
T3	492509	2374	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	80	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	2703	0	0
T12	0	8424	0	0
T25	0	1941	0	0
T32	0	10	0	0
T33	0	4132	0	0
T39	0	1181	0	0
T47	0	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	29262376	0	0
T1	214424	208056	0	0
T2	115088	0	0	0
T3	492509	197384	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	1120	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	68952	0	0
T12	0	204288	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	29262376	0	0
T1	214424	208056	0	0
T2	115088	0	0	0
T3	492509	197384	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	1120	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	68952	0	0
T12	0	204288	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	681344	0	0
T1	214424	5486	0	0
T2	115088	0	0	0
T3	492509	2374	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	80	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	2703	0	0
T12	0	8424	0	0
T25	0	1941	0	0
T32	0	10	0	0
T33	0	4132	0	0
T39	0	1181	0	0
T47	0	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	681344	0	0
T1	214424	5486	0	0
T2	115088	0	0	0
T3	492509	2374	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	80	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	2703	0	0
T12	0	8424	0	0
T25	0	1941	0	0
T32	0	10	0	0
T33	0	4132	0	0
T39	0	1181	0	0
T47	0	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	681344	0	0
T1	214424	5486	0	0
T2	115088	0	0	0
T3	492509	2374	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	80	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	2703	0	0
T12	0	8424	0	0
T25	0	1941	0	0
T32	0	10	0	0
T33	0	4132	0	0
T39	0	1181	0	0
T47	0	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	681344	0	0
T1	214424	5486	0	0
T2	115088	0	0	0
T3	492509	2374	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	80	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	2703	0	0
T12	0	8424	0	0
T25	0	1941	0	0
T32	0	10	0	0
T33	0	4132	0	0
T39	0	1181	0	0
T47	0	120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	29262376	0	0
T1	214424	208056	0	0
T2	115088	0	0	0
T3	492509	197384	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	1120	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	68952	0	0
T12	0	204288	0	0
T23	0	13808	0	0
T25	0	121784	0	0
T29	0	24568	0	0
T31	0	504	0	0
T32	0	344	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	681344	0	0
T1	214424	5486	0	0
T2	115088	0	0	0
T3	492509	2374	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	80	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	0	2703	0	0
T12	0	8424	0	0
T25	0	1941	0	0
T32	0	10	0	0
T33	0	4132	0	0
T39	0	1181	0	0
T47	0	120	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T11,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153278707	122582674	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	153278707	820623	0	0
GntImpliesValid_A	153278707	820623	0	0
GrantKnown_A	153278707	122582674	0	0
IdxKnown_A	153278707	122582674	0	0
IndexIsCorrect_A	153278707	820623	0	0
LockArbDecision_A	153278707	0	0	0
NoReadyValidNoGrant_A	153278707	0	0	0
ReadyAndValidImplyGrant_A	153278707	820623	0	0
ReqAndReadyImplyGrant_A	153278707	820623	0	0
ReqImpliesValid_A	153278707	820623	0	0
ReqStaysHighUntilGranted0_M	153278707	0	0	0
RoundRobin_A	153278707	0	0	0
ValidKnown_A	153278707	122582674	0	0
gen_data_port_assertion.DataFlow_A	153278707	820623	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	122582674	0	0
T2	115088	115088	0	0
T3	492509	291537	0	0
T4	80674	80079	0	0
T5	48	48	0	0
T6	1120	0	0	0
T7	19955	19720	0	0
T8	4212	4212	0	0
T9	14798	14798	0	0
T10	24732	24488	0	0
T11	495587	419856	0	0
T12	0	162192	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	820623	0	0
T3	492509	3140	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	0	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	495587	4426	0	0
T12	0	11946	0	0
T25	0	1039	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T33	0	3134	0	0
T38	0	3301	0	0
T44	0	271	0	0
T51	0	388	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	820623	0	0
T3	492509	3140	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	0	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	495587	4426	0	0
T12	0	11946	0	0
T25	0	1039	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T33	0	3134	0	0
T38	0	3301	0	0
T44	0	271	0	0
T51	0	388	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	122582674	0	0
T2	115088	115088	0	0
T3	492509	291537	0	0
T4	80674	80079	0	0
T5	48	48	0	0
T6	1120	0	0	0
T7	19955	19720	0	0
T8	4212	4212	0	0
T9	14798	14798	0	0
T10	24732	24488	0	0
T11	495587	419856	0	0
T12	0	162192	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	122582674	0	0
T2	115088	115088	0	0
T3	492509	291537	0	0
T4	80674	80079	0	0
T5	48	48	0	0
T6	1120	0	0	0
T7	19955	19720	0	0
T8	4212	4212	0	0
T9	14798	14798	0	0
T10	24732	24488	0	0
T11	495587	419856	0	0
T12	0	162192	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	820623	0	0
T3	492509	3140	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	0	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	495587	4426	0	0
T12	0	11946	0	0
T25	0	1039	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T33	0	3134	0	0
T38	0	3301	0	0
T44	0	271	0	0
T51	0	388	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	820623	0	0
T3	492509	3140	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	0	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	495587	4426	0	0
T12	0	11946	0	0
T25	0	1039	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T33	0	3134	0	0
T38	0	3301	0	0
T44	0	271	0	0
T51	0	388	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	820623	0	0
T3	492509	3140	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	0	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	495587	4426	0	0
T12	0	11946	0	0
T25	0	1039	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T33	0	3134	0	0
T38	0	3301	0	0
T44	0	271	0	0
T51	0	388	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	820623	0	0
T3	492509	3140	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	0	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	495587	4426	0	0
T12	0	11946	0	0
T25	0	1039	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T33	0	3134	0	0
T38	0	3301	0	0
T44	0	271	0	0
T51	0	388	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	122582674	0	0
T2	115088	115088	0	0
T3	492509	291537	0	0
T4	80674	80079	0	0
T5	48	48	0	0
T6	1120	0	0	0
T7	19955	19720	0	0
T8	4212	4212	0	0
T9	14798	14798	0	0
T10	24732	24488	0	0
T11	495587	419856	0	0
T12	0	162192	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153278707	820623	0	0
T3	492509	3140	0	0
T4	80674	0	0	0
T5	48	0	0	0
T6	1120	0	0	0
T7	19955	0	0	0
T8	4212	0	0	0
T9	14798	0	0	0
T10	24732	0	0	0
T11	495587	4426	0	0
T12	0	11946	0	0
T25	0	1039	0	0
T26	0	5378	0	0
T28	0	1432	0	0
T31	504	0	0	0
T33	0	3134	0	0
T38	0	3301	0	0
T44	0	271	0	0
T51	0	388	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	474064514	473975559	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	474064514	2320692	0	0
GntImpliesValid_A	474064514	2320692	0	0
GrantKnown_A	474064514	473975559	0	0
IdxKnown_A	474064514	473975559	0	0
IndexIsCorrect_A	474064514	2320692	0	0
LockArbDecision_A	474064514	0	0	0
NoReadyValidNoGrant_A	474064514	0	0	0
ReadyAndValidImplyGrant_A	474064514	2320692	0	0
ReqAndReadyImplyGrant_A	474064514	2320692	0	0
ReqImpliesValid_A	474064514	2320692	0	0
ReqStaysHighUntilGranted0_M	474064514	0	0	0
RoundRobin_A	474064514	6	0	975
ValidKnown_A	474064514	473975559	0	0
gen_data_port_assertion.DataFlow_A	474064514	2320692	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	473975559	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	2320692	0	0
T1	277761	2716	0	0
T2	694174	832	0	0
T3	181068	5485	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	32	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	832	0	0
T10	199171	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	2320692	0	0
T1	277761	2716	0	0
T2	694174	832	0	0
T3	181068	5485	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	32	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	832	0	0
T10	199171	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	473975559	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	473975559	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	2320692	0	0
T1	277761	2716	0	0
T2	694174	832	0	0
T3	181068	5485	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	32	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	832	0	0
T10	199171	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	2320692	0	0
T1	277761	2716	0	0
T2	694174	832	0	0
T3	181068	5485	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	32	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	832	0	0
T10	199171	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	2320692	0	0
T1	277761	2716	0	0
T2	694174	832	0	0
T3	181068	5485	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	32	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	832	0	0
T10	199171	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	2320692	0	0
T1	277761	2716	0	0
T2	694174	832	0	0
T3	181068	5485	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	32	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	832	0	0
T10	199171	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	6	0	975
T12	945126	1	0	1
T15	0	1	0	0
T22	389891	0	0	1
T23	33963	0	0	1
T24	3139	0	0	1
T25	579077	0	0	1
T26	807657	0	0	1
T27	980	0	0	1
T28	98175	0	0	1
T29	36481	0	0	1
T30	1156	0	0	1
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	473975559	0	0
T1	277761	277675	0	0
T2	694174	694096	0	0
T3	181068	180989	0	0
T4	56645	56547	0	0
T5	3036	2960	0	0
T6	7935	7856	0	0
T7	27998	27940	0	0
T8	15332	15255	0	0
T9	18518	18448	0	0
T10	199171	199099	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474064514	2320692	0	0
T1	277761	2716	0	0
T2	694174	832	0	0
T3	181068	5485	0	0
T4	56645	1664	0	0
T5	3036	832	0	0
T6	7935	32	0	0
T7	27998	832	0	0
T8	15332	832	0	0
T9	18518	832	0	0
T10	199171	832	0	0