Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
3645 | 
0 | 
0 | 
| T88 | 
37148 | 
3 | 
0 | 
0 | 
| T89 | 
32343 | 
1 | 
0 | 
0 | 
| T90 | 
5835 | 
49 | 
0 | 
0 | 
| T91 | 
7343 | 
106 | 
0 | 
0 | 
| T92 | 
2301 | 
75 | 
0 | 
0 | 
| T93 | 
10822 | 
2 | 
0 | 
0 | 
| T96 | 
16312 | 
252 | 
0 | 
0 | 
| T98 | 
2955 | 
85 | 
0 | 
0 | 
| T103 | 
5908 | 
32 | 
0 | 
0 | 
| T107 | 
3584 | 
8 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2310 | 
0 | 
0 | 
| T88 | 
37148 | 
51 | 
0 | 
0 | 
| T89 | 
32343 | 
14 | 
0 | 
0 | 
| T109 | 
270963 | 
627 | 
0 | 
0 | 
| T115 | 
9352 | 
8 | 
0 | 
0 | 
| T140 | 
19275 | 
59 | 
0 | 
0 | 
| T141 | 
33406 | 
44 | 
0 | 
0 | 
| T142 | 
7590 | 
49 | 
0 | 
0 | 
| T143 | 
39174 | 
224 | 
0 | 
0 | 
| T144 | 
74442 | 
67 | 
0 | 
0 | 
| T145 | 
35136 | 
39 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2457 | 
0 | 
0 | 
| T88 | 
37148 | 
38 | 
0 | 
0 | 
| T89 | 
32343 | 
16 | 
0 | 
0 | 
| T109 | 
270963 | 
660 | 
0 | 
0 | 
| T115 | 
9352 | 
6 | 
0 | 
0 | 
| T140 | 
19275 | 
87 | 
0 | 
0 | 
| T141 | 
33406 | 
53 | 
0 | 
0 | 
| T142 | 
7590 | 
26 | 
0 | 
0 | 
| T143 | 
39174 | 
283 | 
0 | 
0 | 
| T144 | 
74442 | 
65 | 
0 | 
0 | 
| T145 | 
35136 | 
41 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2992 | 
0 | 
0 | 
| T88 | 
37148 | 
66 | 
0 | 
0 | 
| T89 | 
32343 | 
27 | 
0 | 
0 | 
| T109 | 
270963 | 
654 | 
0 | 
0 | 
| T115 | 
9352 | 
32 | 
0 | 
0 | 
| T140 | 
19275 | 
62 | 
0 | 
0 | 
| T141 | 
33406 | 
100 | 
0 | 
0 | 
| T142 | 
7590 | 
33 | 
0 | 
0 | 
| T143 | 
39174 | 
268 | 
0 | 
0 | 
| T144 | 
74442 | 
188 | 
0 | 
0 | 
| T145 | 
35136 | 
86 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
9768 | 
0 | 
0 | 
| T88 | 
37148 | 
868 | 
0 | 
0 | 
| T89 | 
32343 | 
414 | 
0 | 
0 | 
| T96 | 
16312 | 
2 | 
0 | 
0 | 
| T109 | 
270963 | 
687 | 
0 | 
0 | 
| T115 | 
9352 | 
262 | 
0 | 
0 | 
| T140 | 
19275 | 
67 | 
0 | 
0 | 
| T141 | 
33406 | 
423 | 
0 | 
0 | 
| T142 | 
7590 | 
45 | 
0 | 
0 | 
| T143 | 
39174 | 
254 | 
0 | 
0 | 
| T144 | 
74442 | 
1341 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
10553 | 
0 | 
0 | 
| T88 | 
37148 | 
814 | 
0 | 
0 | 
| T89 | 
32343 | 
373 | 
0 | 
0 | 
| T96 | 
16312 | 
7 | 
0 | 
0 | 
| T109 | 
270963 | 
719 | 
0 | 
0 | 
| T115 | 
9352 | 
160 | 
0 | 
0 | 
| T140 | 
19275 | 
95 | 
0 | 
0 | 
| T141 | 
33406 | 
674 | 
0 | 
0 | 
| T142 | 
7590 | 
7 | 
0 | 
0 | 
| T143 | 
39174 | 
295 | 
0 | 
0 | 
| T144 | 
74442 | 
1550 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
9985 | 
0 | 
0 | 
| T88 | 
37148 | 
878 | 
0 | 
0 | 
| T89 | 
32343 | 
391 | 
0 | 
0 | 
| T109 | 
270963 | 
667 | 
0 | 
0 | 
| T115 | 
9352 | 
208 | 
0 | 
0 | 
| T140 | 
19275 | 
94 | 
0 | 
0 | 
| T141 | 
33406 | 
599 | 
0 | 
0 | 
| T142 | 
7590 | 
3 | 
0 | 
0 | 
| T143 | 
39174 | 
271 | 
0 | 
0 | 
| T144 | 
74442 | 
854 | 
0 | 
0 | 
| T145 | 
35136 | 
1078 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
10246 | 
0 | 
0 | 
| T88 | 
37148 | 
754 | 
0 | 
0 | 
| T89 | 
32343 | 
369 | 
0 | 
0 | 
| T109 | 
270963 | 
654 | 
0 | 
0 | 
| T115 | 
9352 | 
224 | 
0 | 
0 | 
| T140 | 
19275 | 
56 | 
0 | 
0 | 
| T141 | 
33406 | 
551 | 
0 | 
0 | 
| T142 | 
7590 | 
9 | 
0 | 
0 | 
| T143 | 
39174 | 
269 | 
0 | 
0 | 
| T144 | 
74442 | 
1454 | 
0 | 
0 | 
| T145 | 
35136 | 
666 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
11030 | 
0 | 
0 | 
| T88 | 
37148 | 
709 | 
0 | 
0 | 
| T89 | 
32343 | 
537 | 
0 | 
0 | 
| T109 | 
270963 | 
665 | 
0 | 
0 | 
| T115 | 
9352 | 
266 | 
0 | 
0 | 
| T140 | 
19275 | 
76 | 
0 | 
0 | 
| T141 | 
33406 | 
793 | 
0 | 
0 | 
| T142 | 
7590 | 
9 | 
0 | 
0 | 
| T143 | 
39174 | 
275 | 
0 | 
0 | 
| T144 | 
74442 | 
1611 | 
0 | 
0 | 
| T145 | 
35136 | 
927 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
10495 | 
0 | 
0 | 
| T88 | 
37148 | 
676 | 
0 | 
0 | 
| T89 | 
32343 | 
482 | 
0 | 
0 | 
| T109 | 
270963 | 
725 | 
0 | 
0 | 
| T115 | 
9352 | 
241 | 
0 | 
0 | 
| T140 | 
19275 | 
34 | 
0 | 
0 | 
| T141 | 
33406 | 
678 | 
0 | 
0 | 
| T142 | 
7590 | 
23 | 
0 | 
0 | 
| T143 | 
39174 | 
274 | 
0 | 
0 | 
| T144 | 
74442 | 
1372 | 
0 | 
0 | 
| T145 | 
35136 | 
274 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
10203 | 
0 | 
0 | 
| T88 | 
37148 | 
861 | 
0 | 
0 | 
| T89 | 
32343 | 
442 | 
0 | 
0 | 
| T109 | 
270963 | 
614 | 
0 | 
0 | 
| T115 | 
9352 | 
264 | 
0 | 
0 | 
| T140 | 
19275 | 
34 | 
0 | 
0 | 
| T141 | 
33406 | 
480 | 
0 | 
0 | 
| T142 | 
7590 | 
1 | 
0 | 
0 | 
| T143 | 
39174 | 
287 | 
0 | 
0 | 
| T144 | 
74442 | 
1566 | 
0 | 
0 | 
| T145 | 
35136 | 
415 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
9093 | 
0 | 
0 | 
| T88 | 
37148 | 
926 | 
0 | 
0 | 
| T89 | 
32343 | 
278 | 
0 | 
0 | 
| T100 | 
18875 | 
4 | 
0 | 
0 | 
| T109 | 
270963 | 
667 | 
0 | 
0 | 
| T115 | 
9352 | 
7 | 
0 | 
0 | 
| T140 | 
19275 | 
62 | 
0 | 
0 | 
| T141 | 
33406 | 
513 | 
0 | 
0 | 
| T142 | 
7590 | 
20 | 
0 | 
0 | 
| T143 | 
39174 | 
248 | 
0 | 
0 | 
| T144 | 
74442 | 
1240 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
4953 | 
0 | 
0 | 
| T88 | 
37148 | 
226 | 
0 | 
0 | 
| T89 | 
32343 | 
144 | 
0 | 
0 | 
| T109 | 
270963 | 
665 | 
0 | 
0 | 
| T115 | 
9352 | 
113 | 
0 | 
0 | 
| T140 | 
19275 | 
98 | 
0 | 
0 | 
| T141 | 
33406 | 
276 | 
0 | 
0 | 
| T142 | 
7590 | 
20 | 
0 | 
0 | 
| T143 | 
39174 | 
264 | 
0 | 
0 | 
| T144 | 
74442 | 
352 | 
0 | 
0 | 
| T145 | 
35136 | 
255 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5110 | 
0 | 
0 | 
| T88 | 
37148 | 
251 | 
0 | 
0 | 
| T89 | 
32343 | 
126 | 
0 | 
0 | 
| T109 | 
270963 | 
701 | 
0 | 
0 | 
| T115 | 
9352 | 
1 | 
0 | 
0 | 
| T118 | 
36196 | 
201 | 
0 | 
0 | 
| T140 | 
19275 | 
65 | 
0 | 
0 | 
| T141 | 
33406 | 
209 | 
0 | 
0 | 
| T143 | 
39174 | 
334 | 
0 | 
0 | 
| T144 | 
74442 | 
468 | 
0 | 
0 | 
| T145 | 
35136 | 
385 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5239 | 
0 | 
0 | 
| T88 | 
37148 | 
140 | 
0 | 
0 | 
| T89 | 
32343 | 
125 | 
0 | 
0 | 
| T109 | 
270963 | 
652 | 
0 | 
0 | 
| T115 | 
9352 | 
112 | 
0 | 
0 | 
| T140 | 
19275 | 
105 | 
0 | 
0 | 
| T141 | 
33406 | 
278 | 
0 | 
0 | 
| T142 | 
7590 | 
21 | 
0 | 
0 | 
| T143 | 
39174 | 
298 | 
0 | 
0 | 
| T144 | 
74442 | 
582 | 
0 | 
0 | 
| T145 | 
35136 | 
357 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5634 | 
0 | 
0 | 
| T88 | 
37148 | 
391 | 
0 | 
0 | 
| T89 | 
32343 | 
223 | 
0 | 
0 | 
| T109 | 
270963 | 
613 | 
0 | 
0 | 
| T115 | 
9352 | 
52 | 
0 | 
0 | 
| T140 | 
19275 | 
78 | 
0 | 
0 | 
| T141 | 
33406 | 
230 | 
0 | 
0 | 
| T142 | 
7590 | 
5 | 
0 | 
0 | 
| T143 | 
39174 | 
228 | 
0 | 
0 | 
| T144 | 
74442 | 
771 | 
0 | 
0 | 
| T145 | 
35136 | 
259 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5192 | 
0 | 
0 | 
| T88 | 
37148 | 
221 | 
0 | 
0 | 
| T89 | 
32343 | 
119 | 
0 | 
0 | 
| T109 | 
270963 | 
684 | 
0 | 
0 | 
| T115 | 
9352 | 
6 | 
0 | 
0 | 
| T140 | 
19275 | 
16 | 
0 | 
0 | 
| T141 | 
33406 | 
142 | 
0 | 
0 | 
| T142 | 
7590 | 
37 | 
0 | 
0 | 
| T143 | 
39174 | 
279 | 
0 | 
0 | 
| T144 | 
74442 | 
341 | 
0 | 
0 | 
| T145 | 
35136 | 
348 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5249 | 
0 | 
0 | 
| T88 | 
37148 | 
194 | 
0 | 
0 | 
| T89 | 
32343 | 
129 | 
0 | 
0 | 
| T109 | 
270963 | 
691 | 
0 | 
0 | 
| T115 | 
9352 | 
58 | 
0 | 
0 | 
| T140 | 
19275 | 
61 | 
0 | 
0 | 
| T141 | 
33406 | 
233 | 
0 | 
0 | 
| T142 | 
7590 | 
28 | 
0 | 
0 | 
| T143 | 
39174 | 
278 | 
0 | 
0 | 
| T144 | 
74442 | 
527 | 
0 | 
0 | 
| T145 | 
35136 | 
474 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5422 | 
0 | 
0 | 
| T88 | 
37148 | 
207 | 
0 | 
0 | 
| T89 | 
32343 | 
141 | 
0 | 
0 | 
| T100 | 
18875 | 
5 | 
0 | 
0 | 
| T109 | 
270963 | 
699 | 
0 | 
0 | 
| T115 | 
9352 | 
98 | 
0 | 
0 | 
| T140 | 
19275 | 
64 | 
0 | 
0 | 
| T141 | 
33406 | 
352 | 
0 | 
0 | 
| T142 | 
7590 | 
45 | 
0 | 
0 | 
| T143 | 
39174 | 
285 | 
0 | 
0 | 
| T144 | 
74442 | 
468 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
4994 | 
0 | 
0 | 
| T88 | 
37148 | 
265 | 
0 | 
0 | 
| T89 | 
32343 | 
167 | 
0 | 
0 | 
| T96 | 
16312 | 
5 | 
0 | 
0 | 
| T109 | 
270963 | 
728 | 
0 | 
0 | 
| T115 | 
9352 | 
89 | 
0 | 
0 | 
| T140 | 
19275 | 
114 | 
0 | 
0 | 
| T141 | 
33406 | 
222 | 
0 | 
0 | 
| T142 | 
7590 | 
15 | 
0 | 
0 | 
| T143 | 
39174 | 
268 | 
0 | 
0 | 
| T144 | 
74442 | 
349 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5581 | 
0 | 
0 | 
| T88 | 
37148 | 
317 | 
0 | 
0 | 
| T89 | 
32343 | 
190 | 
0 | 
0 | 
| T96 | 
16312 | 
3 | 
0 | 
0 | 
| T109 | 
270963 | 
628 | 
0 | 
0 | 
| T115 | 
9352 | 
46 | 
0 | 
0 | 
| T140 | 
19275 | 
61 | 
0 | 
0 | 
| T141 | 
33406 | 
279 | 
0 | 
0 | 
| T142 | 
7590 | 
32 | 
0 | 
0 | 
| T143 | 
39174 | 
254 | 
0 | 
0 | 
| T144 | 
74442 | 
659 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5579 | 
0 | 
0 | 
| T88 | 
37148 | 
254 | 
0 | 
0 | 
| T89 | 
32343 | 
82 | 
0 | 
0 | 
| T109 | 
270963 | 
696 | 
0 | 
0 | 
| T115 | 
9352 | 
119 | 
0 | 
0 | 
| T140 | 
19275 | 
62 | 
0 | 
0 | 
| T141 | 
33406 | 
278 | 
0 | 
0 | 
| T142 | 
7590 | 
46 | 
0 | 
0 | 
| T143 | 
39174 | 
293 | 
0 | 
0 | 
| T144 | 
74442 | 
652 | 
0 | 
0 | 
| T145 | 
35136 | 
290 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5558 | 
0 | 
0 | 
| T88 | 
37148 | 
336 | 
0 | 
0 | 
| T89 | 
32343 | 
118 | 
0 | 
0 | 
| T109 | 
270963 | 
639 | 
0 | 
0 | 
| T115 | 
9352 | 
15 | 
0 | 
0 | 
| T140 | 
19275 | 
69 | 
0 | 
0 | 
| T141 | 
33406 | 
191 | 
0 | 
0 | 
| T142 | 
7590 | 
12 | 
0 | 
0 | 
| T143 | 
39174 | 
293 | 
0 | 
0 | 
| T144 | 
74442 | 
649 | 
0 | 
0 | 
| T145 | 
35136 | 
261 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5201 | 
0 | 
0 | 
| T88 | 
37148 | 
290 | 
0 | 
0 | 
| T89 | 
32343 | 
165 | 
0 | 
0 | 
| T109 | 
270963 | 
696 | 
0 | 
0 | 
| T115 | 
9352 | 
10 | 
0 | 
0 | 
| T140 | 
19275 | 
42 | 
0 | 
0 | 
| T141 | 
33406 | 
320 | 
0 | 
0 | 
| T142 | 
7590 | 
13 | 
0 | 
0 | 
| T143 | 
39174 | 
263 | 
0 | 
0 | 
| T144 | 
74442 | 
403 | 
0 | 
0 | 
| T145 | 
35136 | 
285 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5933 | 
0 | 
0 | 
| T88 | 
37148 | 
286 | 
0 | 
0 | 
| T89 | 
32343 | 
51 | 
0 | 
0 | 
| T109 | 
270963 | 
674 | 
0 | 
0 | 
| T115 | 
9352 | 
115 | 
0 | 
0 | 
| T140 | 
19275 | 
60 | 
0 | 
0 | 
| T141 | 
33406 | 
403 | 
0 | 
0 | 
| T142 | 
7590 | 
13 | 
0 | 
0 | 
| T143 | 
39174 | 
281 | 
0 | 
0 | 
| T144 | 
74442 | 
689 | 
0 | 
0 | 
| T145 | 
35136 | 
346 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5218 | 
0 | 
0 | 
| T88 | 
37148 | 
315 | 
0 | 
0 | 
| T89 | 
32343 | 
145 | 
0 | 
0 | 
| T109 | 
270963 | 
703 | 
0 | 
0 | 
| T115 | 
9352 | 
29 | 
0 | 
0 | 
| T140 | 
19275 | 
57 | 
0 | 
0 | 
| T141 | 
33406 | 
291 | 
0 | 
0 | 
| T142 | 
7590 | 
27 | 
0 | 
0 | 
| T143 | 
39174 | 
281 | 
0 | 
0 | 
| T144 | 
74442 | 
528 | 
0 | 
0 | 
| T145 | 
35136 | 
306 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5566 | 
0 | 
0 | 
| T88 | 
37148 | 
263 | 
0 | 
0 | 
| T89 | 
32343 | 
132 | 
0 | 
0 | 
| T109 | 
270963 | 
711 | 
0 | 
0 | 
| T115 | 
9352 | 
47 | 
0 | 
0 | 
| T140 | 
19275 | 
75 | 
0 | 
0 | 
| T141 | 
33406 | 
341 | 
0 | 
0 | 
| T142 | 
7590 | 
36 | 
0 | 
0 | 
| T143 | 
39174 | 
273 | 
0 | 
0 | 
| T144 | 
74442 | 
552 | 
0 | 
0 | 
| T145 | 
35136 | 
213 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5212 | 
0 | 
0 | 
| T88 | 
37148 | 
298 | 
0 | 
0 | 
| T89 | 
32343 | 
165 | 
0 | 
0 | 
| T109 | 
270963 | 
649 | 
0 | 
0 | 
| T115 | 
9352 | 
8 | 
0 | 
0 | 
| T140 | 
19275 | 
74 | 
0 | 
0 | 
| T141 | 
33406 | 
147 | 
0 | 
0 | 
| T142 | 
7590 | 
26 | 
0 | 
0 | 
| T143 | 
39174 | 
284 | 
0 | 
0 | 
| T144 | 
74442 | 
586 | 
0 | 
0 | 
| T145 | 
35136 | 
266 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5287 | 
0 | 
0 | 
| T88 | 
37148 | 
274 | 
0 | 
0 | 
| T89 | 
32343 | 
145 | 
0 | 
0 | 
| T109 | 
270963 | 
658 | 
0 | 
0 | 
| T115 | 
9352 | 
89 | 
0 | 
0 | 
| T140 | 
19275 | 
82 | 
0 | 
0 | 
| T141 | 
33406 | 
178 | 
0 | 
0 | 
| T142 | 
7590 | 
26 | 
0 | 
0 | 
| T143 | 
39174 | 
295 | 
0 | 
0 | 
| T144 | 
74442 | 
455 | 
0 | 
0 | 
| T145 | 
35136 | 
231 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5446 | 
0 | 
0 | 
| T88 | 
37148 | 
214 | 
0 | 
0 | 
| T89 | 
32343 | 
93 | 
0 | 
0 | 
| T100 | 
18875 | 
4 | 
0 | 
0 | 
| T109 | 
270963 | 
669 | 
0 | 
0 | 
| T115 | 
9352 | 
82 | 
0 | 
0 | 
| T140 | 
19275 | 
50 | 
0 | 
0 | 
| T141 | 
33406 | 
328 | 
0 | 
0 | 
| T142 | 
7590 | 
12 | 
0 | 
0 | 
| T143 | 
39174 | 
297 | 
0 | 
0 | 
| T144 | 
74442 | 
329 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5140 | 
0 | 
0 | 
| T88 | 
37148 | 
295 | 
0 | 
0 | 
| T89 | 
32343 | 
126 | 
0 | 
0 | 
| T109 | 
270963 | 
656 | 
0 | 
0 | 
| T115 | 
9352 | 
5 | 
0 | 
0 | 
| T140 | 
19275 | 
69 | 
0 | 
0 | 
| T141 | 
33406 | 
379 | 
0 | 
0 | 
| T142 | 
7590 | 
1 | 
0 | 
0 | 
| T143 | 
39174 | 
236 | 
0 | 
0 | 
| T144 | 
74442 | 
437 | 
0 | 
0 | 
| T145 | 
35136 | 
157 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5443 | 
0 | 
0 | 
| T88 | 
37148 | 
179 | 
0 | 
0 | 
| T89 | 
32343 | 
121 | 
0 | 
0 | 
| T109 | 
270963 | 
620 | 
0 | 
0 | 
| T115 | 
9352 | 
49 | 
0 | 
0 | 
| T140 | 
19275 | 
33 | 
0 | 
0 | 
| T141 | 
33406 | 
278 | 
0 | 
0 | 
| T142 | 
7590 | 
41 | 
0 | 
0 | 
| T143 | 
39174 | 
271 | 
0 | 
0 | 
| T144 | 
74442 | 
711 | 
0 | 
0 | 
| T145 | 
35136 | 
237 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5414 | 
0 | 
0 | 
| T88 | 
37148 | 
211 | 
0 | 
0 | 
| T89 | 
32343 | 
153 | 
0 | 
0 | 
| T109 | 
270963 | 
691 | 
0 | 
0 | 
| T115 | 
9352 | 
62 | 
0 | 
0 | 
| T140 | 
19275 | 
48 | 
0 | 
0 | 
| T141 | 
33406 | 
225 | 
0 | 
0 | 
| T142 | 
7590 | 
42 | 
0 | 
0 | 
| T143 | 
39174 | 
302 | 
0 | 
0 | 
| T144 | 
74442 | 
740 | 
0 | 
0 | 
| T145 | 
35136 | 
305 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5170 | 
0 | 
0 | 
| T88 | 
37148 | 
287 | 
0 | 
0 | 
| T89 | 
32343 | 
233 | 
0 | 
0 | 
| T109 | 
270963 | 
622 | 
0 | 
0 | 
| T115 | 
9352 | 
25 | 
0 | 
0 | 
| T140 | 
19275 | 
60 | 
0 | 
0 | 
| T141 | 
33406 | 
259 | 
0 | 
0 | 
| T142 | 
7590 | 
10 | 
0 | 
0 | 
| T143 | 
39174 | 
216 | 
0 | 
0 | 
| T144 | 
74442 | 
474 | 
0 | 
0 | 
| T145 | 
35136 | 
245 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5504 | 
0 | 
0 | 
| T88 | 
37148 | 
241 | 
0 | 
0 | 
| T89 | 
32343 | 
156 | 
0 | 
0 | 
| T100 | 
18875 | 
2 | 
0 | 
0 | 
| T109 | 
270963 | 
649 | 
0 | 
0 | 
| T115 | 
9352 | 
60 | 
0 | 
0 | 
| T140 | 
19275 | 
27 | 
0 | 
0 | 
| T141 | 
33406 | 
403 | 
0 | 
0 | 
| T142 | 
7590 | 
8 | 
0 | 
0 | 
| T143 | 
39174 | 
205 | 
0 | 
0 | 
| T144 | 
74442 | 
494 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
5151 | 
0 | 
0 | 
| T88 | 
37148 | 
353 | 
0 | 
0 | 
| T89 | 
32343 | 
107 | 
0 | 
0 | 
| T109 | 
270963 | 
660 | 
0 | 
0 | 
| T115 | 
9352 | 
62 | 
0 | 
0 | 
| T140 | 
19275 | 
41 | 
0 | 
0 | 
| T141 | 
33406 | 
199 | 
0 | 
0 | 
| T142 | 
7590 | 
67 | 
0 | 
0 | 
| T143 | 
39174 | 
307 | 
0 | 
0 | 
| T144 | 
74442 | 
373 | 
0 | 
0 | 
| T145 | 
35136 | 
276 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2727 | 
0 | 
0 | 
| T88 | 
37148 | 
39 | 
0 | 
0 | 
| T89 | 
32343 | 
34 | 
0 | 
0 | 
| T96 | 
16312 | 
3 | 
0 | 
0 | 
| T109 | 
270963 | 
652 | 
0 | 
0 | 
| T115 | 
9352 | 
13 | 
0 | 
0 | 
| T140 | 
19275 | 
78 | 
0 | 
0 | 
| T141 | 
33406 | 
76 | 
0 | 
0 | 
| T143 | 
39174 | 
280 | 
0 | 
0 | 
| T144 | 
74442 | 
132 | 
0 | 
0 | 
| T145 | 
35136 | 
71 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2740 | 
0 | 
0 | 
| T88 | 
37148 | 
69 | 
0 | 
0 | 
| T89 | 
32343 | 
30 | 
0 | 
0 | 
| T109 | 
270963 | 
716 | 
0 | 
0 | 
| T115 | 
9352 | 
16 | 
0 | 
0 | 
| T140 | 
19275 | 
55 | 
0 | 
0 | 
| T141 | 
33406 | 
50 | 
0 | 
0 | 
| T142 | 
7590 | 
13 | 
0 | 
0 | 
| T143 | 
39174 | 
284 | 
0 | 
0 | 
| T144 | 
74442 | 
113 | 
0 | 
0 | 
| T145 | 
35136 | 
37 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2569 | 
0 | 
0 | 
| T88 | 
37148 | 
49 | 
0 | 
0 | 
| T89 | 
32343 | 
7 | 
0 | 
0 | 
| T109 | 
270963 | 
676 | 
0 | 
0 | 
| T115 | 
9352 | 
11 | 
0 | 
0 | 
| T140 | 
19275 | 
69 | 
0 | 
0 | 
| T141 | 
33406 | 
57 | 
0 | 
0 | 
| T142 | 
7590 | 
27 | 
0 | 
0 | 
| T143 | 
39174 | 
277 | 
0 | 
0 | 
| T144 | 
74442 | 
114 | 
0 | 
0 | 
| T145 | 
35136 | 
51 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2616 | 
0 | 
0 | 
| T88 | 
37148 | 
37 | 
0 | 
0 | 
| T89 | 
32343 | 
16 | 
0 | 
0 | 
| T109 | 
270963 | 
674 | 
0 | 
0 | 
| T115 | 
9352 | 
9 | 
0 | 
0 | 
| T140 | 
19275 | 
88 | 
0 | 
0 | 
| T141 | 
33406 | 
60 | 
0 | 
0 | 
| T142 | 
7590 | 
32 | 
0 | 
0 | 
| T143 | 
39174 | 
249 | 
0 | 
0 | 
| T144 | 
74442 | 
107 | 
0 | 
0 | 
| T145 | 
35136 | 
84 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
3188 | 
0 | 
0 | 
| T88 | 
37148 | 
94 | 
0 | 
0 | 
| T89 | 
32343 | 
56 | 
0 | 
0 | 
| T109 | 
270963 | 
733 | 
0 | 
0 | 
| T115 | 
9352 | 
25 | 
0 | 
0 | 
| T140 | 
19275 | 
33 | 
0 | 
0 | 
| T141 | 
33406 | 
85 | 
0 | 
0 | 
| T142 | 
7590 | 
33 | 
0 | 
0 | 
| T143 | 
39174 | 
320 | 
0 | 
0 | 
| T144 | 
74442 | 
195 | 
0 | 
0 | 
| T145 | 
35136 | 
103 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
4400 | 
0 | 
0 | 
| T15 | 
958346 | 
37 | 
0 | 
0 | 
| T57 | 
1137 | 
0 | 
0 | 
0 | 
| T88 | 
0 | 
124 | 
0 | 
0 | 
| T89 | 
0 | 
112 | 
0 | 
0 | 
| T95 | 
623138 | 
0 | 
0 | 
0 | 
| T146 | 
0 | 
44 | 
0 | 
0 | 
| T147 | 
0 | 
32 | 
0 | 
0 | 
| T148 | 
0 | 
51 | 
0 | 
0 | 
| T149 | 
0 | 
29 | 
0 | 
0 | 
| T150 | 
0 | 
29 | 
0 | 
0 | 
| T151 | 
0 | 
45 | 
0 | 
0 | 
| T152 | 
0 | 
34 | 
0 | 
0 | 
| T153 | 
873966 | 
0 | 
0 | 
0 | 
| T154 | 
17941 | 
0 | 
0 | 
0 | 
| T155 | 
97520 | 
0 | 
0 | 
0 | 
| T156 | 
208733 | 
0 | 
0 | 
0 | 
| T157 | 
17169 | 
0 | 
0 | 
0 | 
| T158 | 
780520 | 
0 | 
0 | 
0 | 
| T159 | 
182092 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2823 | 
0 | 
0 | 
| T88 | 
37148 | 
68 | 
0 | 
0 | 
| T89 | 
32343 | 
27 | 
0 | 
0 | 
| T96 | 
16312 | 
8 | 
0 | 
0 | 
| T109 | 
270963 | 
720 | 
0 | 
0 | 
| T115 | 
9352 | 
12 | 
0 | 
0 | 
| T140 | 
19275 | 
53 | 
0 | 
0 | 
| T141 | 
33406 | 
79 | 
0 | 
0 | 
| T142 | 
7590 | 
12 | 
0 | 
0 | 
| T143 | 
39174 | 
290 | 
0 | 
0 | 
| T144 | 
74442 | 
112 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2690 | 
0 | 
0 | 
| T88 | 
37148 | 
45 | 
0 | 
0 | 
| T89 | 
32343 | 
20 | 
0 | 
0 | 
| T109 | 
270963 | 
700 | 
0 | 
0 | 
| T115 | 
9352 | 
4 | 
0 | 
0 | 
| T140 | 
19275 | 
79 | 
0 | 
0 | 
| T141 | 
33406 | 
51 | 
0 | 
0 | 
| T142 | 
7590 | 
32 | 
0 | 
0 | 
| T143 | 
39174 | 
261 | 
0 | 
0 | 
| T144 | 
74442 | 
151 | 
0 | 
0 | 
| T145 | 
35136 | 
58 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2298 | 
0 | 
0 | 
| T88 | 
37148 | 
37 | 
0 | 
0 | 
| T89 | 
32343 | 
12 | 
0 | 
0 | 
| T109 | 
270963 | 
645 | 
0 | 
0 | 
| T115 | 
9352 | 
2 | 
0 | 
0 | 
| T140 | 
19275 | 
59 | 
0 | 
0 | 
| T141 | 
33406 | 
49 | 
0 | 
0 | 
| T142 | 
7590 | 
17 | 
0 | 
0 | 
| T143 | 
39174 | 
285 | 
0 | 
0 | 
| T144 | 
74442 | 
86 | 
0 | 
0 | 
| T145 | 
35136 | 
55 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2549 | 
0 | 
0 | 
| T88 | 
37148 | 
31 | 
0 | 
0 | 
| T89 | 
32343 | 
6 | 
0 | 
0 | 
| T109 | 
270963 | 
719 | 
0 | 
0 | 
| T115 | 
9352 | 
2 | 
0 | 
0 | 
| T140 | 
19275 | 
69 | 
0 | 
0 | 
| T141 | 
33406 | 
39 | 
0 | 
0 | 
| T142 | 
7590 | 
15 | 
0 | 
0 | 
| T143 | 
39174 | 
286 | 
0 | 
0 | 
| T144 | 
74442 | 
59 | 
0 | 
0 | 
| T145 | 
35136 | 
42 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2348 | 
0 | 
0 | 
| T88 | 
37148 | 
36 | 
0 | 
0 | 
| T89 | 
32343 | 
14 | 
0 | 
0 | 
| T109 | 
270963 | 
612 | 
0 | 
0 | 
| T115 | 
9352 | 
5 | 
0 | 
0 | 
| T140 | 
19275 | 
55 | 
0 | 
0 | 
| T141 | 
33406 | 
45 | 
0 | 
0 | 
| T142 | 
7590 | 
3 | 
0 | 
0 | 
| T143 | 
39174 | 
264 | 
0 | 
0 | 
| T144 | 
74442 | 
90 | 
0 | 
0 | 
| T145 | 
35136 | 
55 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2401 | 
0 | 
0 | 
| T88 | 
37148 | 
20 | 
0 | 
0 | 
| T89 | 
32343 | 
21 | 
0 | 
0 | 
| T109 | 
270963 | 
695 | 
0 | 
0 | 
| T115 | 
9352 | 
7 | 
0 | 
0 | 
| T140 | 
19275 | 
56 | 
0 | 
0 | 
| T141 | 
33406 | 
49 | 
0 | 
0 | 
| T142 | 
7590 | 
27 | 
0 | 
0 | 
| T143 | 
39174 | 
241 | 
0 | 
0 | 
| T144 | 
74442 | 
53 | 
0 | 
0 | 
| T145 | 
35136 | 
37 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
3116 | 
0 | 
0 | 
| T88 | 
37148 | 
81 | 
0 | 
0 | 
| T89 | 
32343 | 
65 | 
0 | 
0 | 
| T109 | 
270963 | 
617 | 
0 | 
0 | 
| T115 | 
9352 | 
34 | 
0 | 
0 | 
| T140 | 
19275 | 
48 | 
0 | 
0 | 
| T141 | 
33406 | 
112 | 
0 | 
0 | 
| T142 | 
7590 | 
35 | 
0 | 
0 | 
| T143 | 
39174 | 
220 | 
0 | 
0 | 
| T144 | 
74442 | 
132 | 
0 | 
0 | 
| T145 | 
35136 | 
112 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2453 | 
0 | 
0 | 
| T88 | 
37148 | 
43 | 
0 | 
0 | 
| T89 | 
32343 | 
14 | 
0 | 
0 | 
| T109 | 
270963 | 
670 | 
0 | 
0 | 
| T115 | 
9352 | 
12 | 
0 | 
0 | 
| T140 | 
19275 | 
43 | 
0 | 
0 | 
| T141 | 
33406 | 
37 | 
0 | 
0 | 
| T142 | 
7590 | 
35 | 
0 | 
0 | 
| T143 | 
39174 | 
240 | 
0 | 
0 | 
| T144 | 
74442 | 
72 | 
0 | 
0 | 
| T145 | 
35136 | 
29 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
3101 | 
0 | 
0 | 
| T88 | 
37148 | 
102 | 
0 | 
0 | 
| T89 | 
32343 | 
49 | 
0 | 
0 | 
| T109 | 
270963 | 
627 | 
0 | 
0 | 
| T115 | 
9352 | 
11 | 
0 | 
0 | 
| T140 | 
19275 | 
75 | 
0 | 
0 | 
| T141 | 
33406 | 
110 | 
0 | 
0 | 
| T142 | 
7590 | 
16 | 
0 | 
0 | 
| T143 | 
39174 | 
230 | 
0 | 
0 | 
| T144 | 
74442 | 
219 | 
0 | 
0 | 
| T145 | 
35136 | 
87 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2671 | 
0 | 
0 | 
| T88 | 
37148 | 
72 | 
0 | 
0 | 
| T89 | 
32343 | 
43 | 
0 | 
0 | 
| T109 | 
270963 | 
629 | 
0 | 
0 | 
| T115 | 
9352 | 
15 | 
0 | 
0 | 
| T118 | 
36196 | 
250 | 
0 | 
0 | 
| T140 | 
19275 | 
27 | 
0 | 
0 | 
| T141 | 
33406 | 
66 | 
0 | 
0 | 
| T143 | 
39174 | 
285 | 
0 | 
0 | 
| T144 | 
74442 | 
112 | 
0 | 
0 | 
| T145 | 
35136 | 
64 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2632 | 
0 | 
0 | 
| T88 | 
37148 | 
51 | 
0 | 
0 | 
| T89 | 
32343 | 
32 | 
0 | 
0 | 
| T109 | 
270963 | 
734 | 
0 | 
0 | 
| T115 | 
9352 | 
15 | 
0 | 
0 | 
| T140 | 
19275 | 
90 | 
0 | 
0 | 
| T141 | 
33406 | 
35 | 
0 | 
0 | 
| T142 | 
7590 | 
23 | 
0 | 
0 | 
| T143 | 
39174 | 
250 | 
0 | 
0 | 
| T144 | 
74442 | 
84 | 
0 | 
0 | 
| T145 | 
35136 | 
24 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2363 | 
0 | 
0 | 
| T88 | 
37148 | 
40 | 
0 | 
0 | 
| T89 | 
32343 | 
33 | 
0 | 
0 | 
| T109 | 
270963 | 
633 | 
0 | 
0 | 
| T115 | 
9352 | 
9 | 
0 | 
0 | 
| T140 | 
19275 | 
56 | 
0 | 
0 | 
| T141 | 
33406 | 
35 | 
0 | 
0 | 
| T142 | 
7590 | 
53 | 
0 | 
0 | 
| T143 | 
39174 | 
265 | 
0 | 
0 | 
| T144 | 
74442 | 
89 | 
0 | 
0 | 
| T145 | 
35136 | 
49 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2261 | 
0 | 
0 | 
| T88 | 
37148 | 
31 | 
0 | 
0 | 
| T89 | 
32343 | 
22 | 
0 | 
0 | 
| T109 | 
270963 | 
594 | 
0 | 
0 | 
| T115 | 
9352 | 
16 | 
0 | 
0 | 
| T140 | 
19275 | 
46 | 
0 | 
0 | 
| T141 | 
33406 | 
34 | 
0 | 
0 | 
| T142 | 
7590 | 
23 | 
0 | 
0 | 
| T143 | 
39174 | 
268 | 
0 | 
0 | 
| T144 | 
74442 | 
73 | 
0 | 
0 | 
| T145 | 
35136 | 
42 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2484 | 
0 | 
0 | 
| T88 | 
37148 | 
43 | 
0 | 
0 | 
| T89 | 
32343 | 
5 | 
0 | 
0 | 
| T109 | 
270963 | 
626 | 
0 | 
0 | 
| T115 | 
9352 | 
2 | 
0 | 
0 | 
| T140 | 
19275 | 
104 | 
0 | 
0 | 
| T141 | 
33406 | 
38 | 
0 | 
0 | 
| T142 | 
7590 | 
2 | 
0 | 
0 | 
| T143 | 
39174 | 
287 | 
0 | 
0 | 
| T144 | 
74442 | 
72 | 
0 | 
0 | 
| T145 | 
35136 | 
45 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2553 | 
0 | 
0 | 
| T88 | 
37148 | 
33 | 
0 | 
0 | 
| T89 | 
32343 | 
28 | 
0 | 
0 | 
| T109 | 
270963 | 
704 | 
0 | 
0 | 
| T115 | 
9352 | 
4 | 
0 | 
0 | 
| T140 | 
19275 | 
50 | 
0 | 
0 | 
| T141 | 
33406 | 
39 | 
0 | 
0 | 
| T142 | 
7590 | 
44 | 
0 | 
0 | 
| T143 | 
39174 | 
245 | 
0 | 
0 | 
| T144 | 
74442 | 
103 | 
0 | 
0 | 
| T145 | 
35136 | 
41 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
476603646 | 
2580 | 
0 | 
0 | 
| T88 | 
37148 | 
50 | 
0 | 
0 | 
| T89 | 
32343 | 
25 | 
0 | 
0 | 
| T109 | 
270963 | 
683 | 
0 | 
0 | 
| T115 | 
9352 | 
8 | 
0 | 
0 | 
| T140 | 
19275 | 
59 | 
0 | 
0 | 
| T141 | 
33406 | 
26 | 
0 | 
0 | 
| T142 | 
7590 | 
32 | 
0 | 
0 | 
| T143 | 
39174 | 
276 | 
0 | 
0 | 
| T144 | 
74442 | 
83 | 
0 | 
0 | 
| T145 | 
35136 | 
68 | 
0 | 
0 |