Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3362367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4109457

1

T1

878

T2

2

T3

15397

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4104570	1			T1	3		T2	1		T3	28970
values[0x0]	1682703	1			T1	442		T2	5		T3	459
values[0x1]	1684551	1			T1	437		T2	4		T3	454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2391913	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5079911

1

T1

881

T2

3

T3

18347

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27210	1			T3	125		T4	18		T6	34
valid_sources[0x01]	26264	1			T3	122		T4	11		T6	47
valid_sources[0x02]	28141	1			T3	116		T4	12		T6	25
valid_sources[0x03]	25812	1			T3	122		T4	14		T6	48
valid_sources[0x04]	26084	1			T3	115		T4	17		T6	23
valid_sources[0x05]	29123	1			T3	112		T4	7		T6	53
valid_sources[0x06]	30629	1			T3	116		T4	11		T6	28
valid_sources[0x07]	28414	1			T3	120		T4	9		T6	23
valid_sources[0x08]	31542	1			T3	110		T4	17		T6	23
valid_sources[0x09]	27431	1			T3	120		T4	18		T6	20
valid_sources[0x0a]	28573	1			T3	103		T4	14		T6	32
valid_sources[0x0b]	27004	1			T3	126		T4	13		T6	29
valid_sources[0x0c]	29578	1			T3	88		T4	16		T6	33
valid_sources[0x0d]	29869	1			T3	109		T4	6		T6	26
valid_sources[0x0e]	26103	1			T3	119		T4	9		T6	49
valid_sources[0x0f]	27799	1			T3	128		T4	7		T6	42
valid_sources[0x10]	27798	1			T3	130		T4	6		T6	44
valid_sources[0x11]	30384	1			T3	111		T4	19		T6	18
valid_sources[0x12]	28746	1			T3	122		T4	20		T6	22
valid_sources[0x13]	28689	1			T3	132		T4	11		T6	30
valid_sources[0x14]	29876	1			T3	119		T4	10		T6	38
valid_sources[0x15]	26922	1			T3	109		T4	15		T5	452
valid_sources[0x16]	28803	1			T3	114		T4	14		T6	41
valid_sources[0x17]	40753	1			T3	116		T4	9		T6	19
valid_sources[0x18]	40010	1			T3	118		T4	9		T6	20
valid_sources[0x19]	28076	1			T3	123		T4	10		T6	33
valid_sources[0x1a]	30883	1			T3	138		T4	15		T6	29
valid_sources[0x1b]	30538	1			T3	102		T4	13		T6	50
valid_sources[0x1c]	29160	1			T3	121		T4	12		T6	30
valid_sources[0x1d]	35426	1			T3	118		T4	13		T6	50
valid_sources[0x1e]	29744	1			T2	1		T3	135		T4	18
valid_sources[0x1f]	26127	1			T3	111		T4	7		T6	34
valid_sources[0x20]	31119	1			T3	116		T4	10		T6	16
valid_sources[0x21]	26802	1			T3	116		T4	11		T6	55
valid_sources[0x22]	27580	1			T3	92		T4	12		T6	48
valid_sources[0x23]	24652	1			T3	112		T4	8		T6	47
valid_sources[0x24]	28162	1			T3	102		T4	12		T6	23
valid_sources[0x25]	27346	1			T3	122		T4	10		T6	36
valid_sources[0x26]	26260	1			T3	102		T4	21		T6	61
valid_sources[0x27]	28018	1			T3	108		T4	14		T6	35
valid_sources[0x28]	34171	1			T3	142		T4	9		T6	41
valid_sources[0x29]	29647	1			T3	133		T4	11		T6	20
valid_sources[0x2a]	31988	1			T3	120		T4	12		T6	30
valid_sources[0x2b]	26925	1			T3	145		T4	9		T6	29
valid_sources[0x2c]	26898	1			T3	124		T4	13		T6	25
valid_sources[0x2d]	27163	1			T3	109		T4	13		T6	30
valid_sources[0x2e]	26936	1			T2	1		T3	126		T4	13
valid_sources[0x2f]	33567	1			T3	92		T4	18		T6	36
valid_sources[0x30]	42952	1			T3	116		T4	11		T6	34
valid_sources[0x31]	27025	1			T3	108		T4	8		T6	40
valid_sources[0x32]	32212	1			T3	97		T4	11		T6	35
valid_sources[0x33]	25804	1			T3	110		T4	9		T6	64
valid_sources[0x34]	26190	1			T3	124		T4	9		T6	30
valid_sources[0x35]	33860	1			T3	122		T4	15		T6	12
valid_sources[0x36]	25507	1			T3	131		T4	15		T6	38
valid_sources[0x37]	25507	1			T3	110		T4	6		T6	29
valid_sources[0x38]	26706	1			T3	128		T4	3		T6	31
valid_sources[0x39]	28885	1			T3	115		T4	16		T6	27
valid_sources[0x3a]	28101	1			T3	115		T4	10		T6	33
valid_sources[0x3b]	32019	1			T3	135		T4	14		T6	24
valid_sources[0x3c]	28931	1			T3	110		T4	9		T6	36
valid_sources[0x3d]	27738	1			T3	119		T4	9		T6	30
valid_sources[0x3e]	27484	1			T3	103		T4	14		T6	27
valid_sources[0x3f]	29755	1			T3	126		T4	13		T6	16
valid_sources[0x40]	25490	1			T3	103		T4	12		T6	31
valid_sources[0x41]	29162	1			T3	127		T4	14		T6	34
valid_sources[0x42]	26699	1			T3	107		T4	17		T6	27
valid_sources[0x43]	27801	1			T3	108		T4	4		T6	44
valid_sources[0x44]	33287	1			T3	117		T4	14		T6	22
valid_sources[0x45]	27928	1			T3	128		T4	10		T6	36
valid_sources[0x46]	28335	1			T3	124		T4	17		T6	36
valid_sources[0x47]	28768	1			T3	116		T4	12		T6	31
valid_sources[0x48]	30103	1			T3	111		T4	10		T6	35
valid_sources[0x49]	33887	1			T3	122		T4	10		T6	33
valid_sources[0x4a]	27915	1			T3	122		T4	11		T6	17
valid_sources[0x4b]	28284	1			T3	106		T4	14		T6	26
valid_sources[0x4c]	27398	1			T3	118		T4	13		T6	30
valid_sources[0x4d]	26599	1			T3	93		T4	20		T6	25
valid_sources[0x4e]	27295	1			T3	113		T4	10		T6	33
valid_sources[0x4f]	26086	1			T3	104		T4	21		T6	45
valid_sources[0x50]	30329	1			T3	117		T4	8		T6	38
valid_sources[0x51]	28241	1			T3	109		T4	15		T6	35
valid_sources[0x52]	27208	1			T3	112		T4	14		T6	50
valid_sources[0x53]	29366	1			T3	120		T4	11		T6	30
valid_sources[0x54]	25491	1			T3	117		T4	3		T6	54
valid_sources[0x55]	26921	1			T3	135		T4	18		T6	41
valid_sources[0x56]	27393	1			T3	119		T4	15		T6	21
valid_sources[0x57]	26501	1			T3	115		T4	13		T6	18
valid_sources[0x58]	26951	1			T3	118		T4	15		T6	31
valid_sources[0x59]	29173	1			T3	123		T4	14		T6	34
valid_sources[0x5a]	27858	1			T3	130		T4	13		T6	31
valid_sources[0x5b]	29700	1			T3	114		T4	12		T6	30
valid_sources[0x5c]	27076	1			T2	1		T3	114		T4	10
valid_sources[0x5d]	27715	1			T3	134		T4	10		T6	35
valid_sources[0x5e]	30908	1			T3	118		T4	17		T6	25
valid_sources[0x5f]	52706	1			T3	102		T4	11		T6	31
valid_sources[0x60]	31394	1			T3	121		T4	10		T6	60
valid_sources[0x61]	28101	1			T3	119		T4	9		T6	13
valid_sources[0x62]	30000	1			T3	117		T4	13		T6	44
valid_sources[0x63]	28650	1			T3	128		T4	11		T6	20
valid_sources[0x64]	27594	1			T3	111		T4	15		T6	20
valid_sources[0x65]	31236	1			T3	132		T4	6		T6	21
valid_sources[0x66]	28943	1			T3	127		T4	18		T6	41
valid_sources[0x67]	29124	1			T2	2		T3	123		T4	15
valid_sources[0x68]	27756	1			T3	125		T4	9		T6	50
valid_sources[0x69]	26825	1			T3	115		T4	17		T6	16
valid_sources[0x6a]	28328	1			T3	114		T4	24		T6	39
valid_sources[0x6b]	29653	1			T3	118		T4	18		T6	33
valid_sources[0x6c]	27943	1			T3	110		T4	10		T6	45
valid_sources[0x6d]	27803	1			T3	119		T4	11		T6	25
valid_sources[0x6e]	26967	1			T2	1		T3	119		T4	19
valid_sources[0x6f]	25638	1			T1	430		T3	111		T4	13
valid_sources[0x70]	28135	1			T3	112		T4	13		T6	25
valid_sources[0x71]	27182	1			T2	1		T3	119		T4	12
valid_sources[0x72]	27367	1			T3	114		T4	11		T6	30
valid_sources[0x73]	30152	1			T3	121		T4	13		T6	25
valid_sources[0x74]	24427	1			T3	115		T4	9		T6	15
valid_sources[0x75]	29735	1			T3	136		T4	16		T6	20
valid_sources[0x76]	28448	1			T3	104		T4	11		T6	71
valid_sources[0x77]	29050	1			T3	112		T4	8		T6	54
valid_sources[0x78]	27719	1			T3	105		T4	14		T6	36
valid_sources[0x79]	29832	1			T3	119		T4	9		T6	9
valid_sources[0x7a]	26352	1			T3	113		T4	23		T6	26
valid_sources[0x7b]	27504	1			T3	121		T4	16		T6	27
valid_sources[0x7c]	27341	1			T3	131		T4	8		T6	31
valid_sources[0x7d]	29606	1			T3	133		T4	15		T6	50
valid_sources[0x7e]	27923	1			T3	99		T4	13		T6	55
valid_sources[0x7f]	27820	1			T3	129		T4	15		T6	35
valid_sources[0x80]	28185	1			T3	132		T4	12		T6	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1045089

1

T1

3

T3

14490

T4

300

values[0x0]

all_enables

biggest_size

1542193

1

T1

441

T2

1

T3

458

values[0x1]

all_enables

biggest_size

1522175

1

T1

434

T2

1

T3

449