Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3378947

1

T1

4

T2

8

T3

14486

full_word

4108359

1

T1

878

T2

2

T3

15397

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7486976	1			T1	882		T2	10		T3	29883
auto[TlIntgErrCmd]	107	1			T90	3		T97	3		T98	9
auto[TlIntgErrData]	111	1			T90	3		T97	2		T98	4
auto[TlIntgErrBoth]	112	1			T90	4		T97	5		T98	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4105968

1

T1

3

T2

1

T3

28970

auto[1]

3381338

1

T1

879

T2

9

T3

913

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3060665	1			T2	1		T3	14480		T4	145
auto[TlIntgErrNone]	partial	auto[1]	317980	1			T1	4		T2	7		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	1045163	1			T1	3		T3	14490		T4	300
auto[TlIntgErrNone]	full_word	auto[1]	3063168	1			T1	875		T2	2		T3	907
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T90	1		T97	2		T98	6
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T90	1		T97	1		T98	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T90	1		T165	1		T166	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T163	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T163	3		T167	4		T164	2
auto[TlIntgErrData]	partial	auto[1]	60	1			T90	3		T97	1		T98	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T97	1		T168	1		T169	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T164	1		T162	1		T166	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T90	3		T97	2		T98	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T97	3		T98	6		T163	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T169	1		T170	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T90	1		T161	1		T165	2