Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T11
1	0	Covered	T7,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T11
1	0	Unreachable
1	1	Covered	T7,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	722189419	574771028	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	722189419	3622826	0	0
GntImpliesValid_A	722189419	3622826	0	0
GrantKnown_A	722189419	574771028	0	0
IdxKnown_A	722189419	574771028	0	0
IndexIsCorrect_A	722189419	3622826	0	0
LockArbDecision_A	722189419	0	0	0
NoReadyValidNoGrant_A	722189419	0	0	0
ReadyAndValidImplyGrant_A	722189419	3622826	0	0
ReqAndReadyImplyGrant_A	722189419	3622826	0	0
ReqImpliesValid_A	722189419	3622826	0	0
ReqStaysHighUntilGranted0_M	722189419	0	0	0
RoundRobin_A	722189419	3	0	976
ValidKnown_A	722189419	574771028	0	0
gen_data_port_assertion.DataFlow_A	722189419	3622826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	574771028	0	0
T1	29423	29343	0	0
T2	1385	1297	0	0
T3	480924	480033	0	0
T4	266200	265513	0	0
T5	329157	329092	0	0
T6	393378	391988	0	0
T7	1445257	924860	0	0
T8	722285	431168	0	0
T9	527858	315336	0	0
T10	1829	1772	0	0
T11	812562	398798	0	0
T12	21386	10693	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3622826	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	266200	4823	0	0
T5	329157	832	0	0
T6	393378	9355	0	0
T7	1445257	13272	0	0
T8	722285	8082	0	0
T9	527858	5316	0	0
T10	1829	0	0	0
T11	812562	17723	0	0
T12	21386	832	0	0
T13	17162	304	0	0
T14	0	11265	0	0
T23	41908	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3963	0	0
T27	0	5695	0	0
T28	0	3237	0	0
T29	0	5294	0	0
T36	0	2867	0	0
T39	12644	0	0	0
T45	44368	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3622826	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	266200	4823	0	0
T5	329157	832	0	0
T6	393378	9355	0	0
T7	1445257	13272	0	0
T8	722285	8082	0	0
T9	527858	5316	0	0
T10	1829	0	0	0
T11	812562	17723	0	0
T12	21386	832	0	0
T13	17162	304	0	0
T14	0	11265	0	0
T23	41908	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3963	0	0
T27	0	5695	0	0
T28	0	3237	0	0
T29	0	5294	0	0
T36	0	2867	0	0
T39	12644	0	0	0
T45	44368	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	574771028	0	0
T1	29423	29343	0	0
T2	1385	1297	0	0
T3	480924	480033	0	0
T4	266200	265513	0	0
T5	329157	329092	0	0
T6	393378	391988	0	0
T7	1445257	924860	0	0
T8	722285	431168	0	0
T9	527858	315336	0	0
T10	1829	1772	0	0
T11	812562	398798	0	0
T12	21386	10693	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	574771028	0	0
T1	29423	29343	0	0
T2	1385	1297	0	0
T3	480924	480033	0	0
T4	266200	265513	0	0
T5	329157	329092	0	0
T6	393378	391988	0	0
T7	1445257	924860	0	0
T8	722285	431168	0	0
T9	527858	315336	0	0
T10	1829	1772	0	0
T11	812562	398798	0	0
T12	21386	10693	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3622826	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	266200	4823	0	0
T5	329157	832	0	0
T6	393378	9355	0	0
T7	1445257	13272	0	0
T8	722285	8082	0	0
T9	527858	5316	0	0
T10	1829	0	0	0
T11	812562	17723	0	0
T12	21386	832	0	0
T13	17162	304	0	0
T14	0	11265	0	0
T23	41908	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3963	0	0
T27	0	5695	0	0
T28	0	3237	0	0
T29	0	5294	0	0
T36	0	2867	0	0
T39	12644	0	0	0
T45	44368	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3622826	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	266200	4823	0	0
T5	329157	832	0	0
T6	393378	9355	0	0
T7	1445257	13272	0	0
T8	722285	8082	0	0
T9	527858	5316	0	0
T10	1829	0	0	0
T11	812562	17723	0	0
T12	21386	832	0	0
T13	17162	304	0	0
T14	0	11265	0	0
T23	41908	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3963	0	0
T27	0	5695	0	0
T28	0	3237	0	0
T29	0	5294	0	0
T36	0	2867	0	0
T39	12644	0	0	0
T45	44368	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3622826	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	266200	4823	0	0
T5	329157	832	0	0
T6	393378	9355	0	0
T7	1445257	13272	0	0
T8	722285	8082	0	0
T9	527858	5316	0	0
T10	1829	0	0	0
T11	812562	17723	0	0
T12	21386	832	0	0
T13	17162	304	0	0
T14	0	11265	0	0
T23	41908	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3963	0	0
T27	0	5695	0	0
T28	0	3237	0	0
T29	0	5294	0	0
T36	0	2867	0	0
T39	12644	0	0	0
T45	44368	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3622826	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	266200	4823	0	0
T5	329157	832	0	0
T6	393378	9355	0	0
T7	1445257	13272	0	0
T8	722285	8082	0	0
T9	527858	5316	0	0
T10	1829	0	0	0
T11	812562	17723	0	0
T12	21386	832	0	0
T13	17162	304	0	0
T14	0	11265	0	0
T23	41908	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3963	0	0
T27	0	5695	0	0
T28	0	3237	0	0
T29	0	5294	0	0
T36	0	2867	0	0
T39	12644	0	0	0
T45	44368	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3	0	976
T20	5381	0	0	1
T46	566866	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	9254	0	0	1
T50	19197	0	0	1
T51	14328	0	0	1
T52	1718	0	0	1
T53	810	0	0	1
T54	209493	0	0	1
T55	48798	0	0	1
T56	213492	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	574771028	0	0
T1	29423	29343	0	0
T2	1385	1297	0	0
T3	480924	480033	0	0
T4	266200	265513	0	0
T5	329157	329092	0	0
T6	393378	391988	0	0
T7	1445257	924860	0	0
T8	722285	431168	0	0
T9	527858	315336	0	0
T10	1829	1772	0	0
T11	812562	398798	0	0
T12	21386	10693	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722189419	3622826	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	266200	4823	0	0
T5	329157	832	0	0
T6	393378	9355	0	0
T7	1445257	13272	0	0
T8	722285	8082	0	0
T9	527858	5316	0	0
T10	1829	0	0	0
T11	812562	17723	0	0
T12	21386	832	0	0
T13	17162	304	0	0
T14	0	11265	0	0
T23	41908	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3963	0	0
T27	0	5695	0	0
T28	0	3237	0	0
T29	0	5294	0	0
T36	0	2867	0	0
T39	12644	0	0	0
T45	44368	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T11
1	0	Covered	T7,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T11
1	0	Unreachable
1	1	Covered	T7,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T11
0	0	1	Unreachable
0	0	0	Covered	T7,T8,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	146066511	26086407	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	146066511	571783	0	0
GntImpliesValid_A	146066511	571783	0	0
GrantKnown_A	146066511	26086407	0	0
IdxKnown_A	146066511	26086407	0	0
IndexIsCorrect_A	146066511	571783	0	0
LockArbDecision_A	146066511	0	0	0
NoReadyValidNoGrant_A	146066511	0	0	0
ReadyAndValidImplyGrant_A	146066511	571783	0	0
ReqAndReadyImplyGrant_A	146066511	571783	0	0
ReqImpliesValid_A	146066511	571783	0	0
ReqStaysHighUntilGranted0_M	146066511	0	0	0
RoundRobin_A	146066511	0	0	0
ValidKnown_A	146066511	26086407	0	0
gen_data_port_assertion.DataFlow_A	146066511	571783	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	26086407	0	0
T7	516641	55280	0	0
T8	287706	20744	0	0
T9	211297	0	0	0
T11	406281	83760	0	0
T12	10693	0	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	571783	0	0
T7	516641	2267	0	0
T8	287706	835	0	0
T9	211297	0	0	0
T11	406281	4291	0	0
T12	10693	0	0	0
T13	8581	304	0	0
T14	0	5668	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3447	0	0
T27	0	5695	0	0
T28	0	1921	0	0
T29	0	5294	0	0
T39	12644	0	0	0
T45	44368	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	571783	0	0
T7	516641	2267	0	0
T8	287706	835	0	0
T9	211297	0	0	0
T11	406281	4291	0	0
T12	10693	0	0	0
T13	8581	304	0	0
T14	0	5668	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3447	0	0
T27	0	5695	0	0
T28	0	1921	0	0
T29	0	5294	0	0
T39	12644	0	0	0
T45	44368	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	26086407	0	0
T7	516641	55280	0	0
T8	287706	20744	0	0
T9	211297	0	0	0
T11	406281	83760	0	0
T12	10693	0	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	26086407	0	0
T7	516641	55280	0	0
T8	287706	20744	0	0
T9	211297	0	0	0
T11	406281	83760	0	0
T12	10693	0	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	571783	0	0
T7	516641	2267	0	0
T8	287706	835	0	0
T9	211297	0	0	0
T11	406281	4291	0	0
T12	10693	0	0	0
T13	8581	304	0	0
T14	0	5668	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3447	0	0
T27	0	5695	0	0
T28	0	1921	0	0
T29	0	5294	0	0
T39	12644	0	0	0
T45	44368	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	571783	0	0
T7	516641	2267	0	0
T8	287706	835	0	0
T9	211297	0	0	0
T11	406281	4291	0	0
T12	10693	0	0	0
T13	8581	304	0	0
T14	0	5668	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3447	0	0
T27	0	5695	0	0
T28	0	1921	0	0
T29	0	5294	0	0
T39	12644	0	0	0
T45	44368	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	571783	0	0
T7	516641	2267	0	0
T8	287706	835	0	0
T9	211297	0	0	0
T11	406281	4291	0	0
T12	10693	0	0	0
T13	8581	304	0	0
T14	0	5668	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3447	0	0
T27	0	5695	0	0
T28	0	1921	0	0
T29	0	5294	0	0
T39	12644	0	0	0
T45	44368	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	571783	0	0
T7	516641	2267	0	0
T8	287706	835	0	0
T9	211297	0	0	0
T11	406281	4291	0	0
T12	10693	0	0	0
T13	8581	304	0	0
T14	0	5668	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3447	0	0
T27	0	5695	0	0
T28	0	1921	0	0
T29	0	5294	0	0
T39	12644	0	0	0
T45	44368	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	26086407	0	0
T7	516641	55280	0	0
T8	287706	20744	0	0
T9	211297	0	0	0
T11	406281	83760	0	0
T12	10693	0	0	0
T13	8581	7880	0	0
T14	0	133552	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	54400	0	0
T26	0	80896	0	0
T27	0	159296	0	0
T28	0	41488	0	0
T29	0	138464	0	0
T39	12644	0	0	0
T45	44368	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	571783	0	0
T7	516641	2267	0	0
T8	287706	835	0	0
T9	211297	0	0	0
T11	406281	4291	0	0
T12	10693	0	0	0
T13	8581	304	0	0
T14	0	5668	0	0
T23	20954	0	0	0
T24	18187	0	0	0
T25	0	2411	0	0
T26	0	3447	0	0
T27	0	5695	0	0
T28	0	1921	0	0
T29	0	5294	0	0
T39	12644	0	0	0
T45	44368	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	146066511	118717830	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	146066511	846790	0	0
GntImpliesValid_A	146066511	846790	0	0
GrantKnown_A	146066511	118717830	0	0
IdxKnown_A	146066511	118717830	0	0
IndexIsCorrect_A	146066511	846790	0	0
LockArbDecision_A	146066511	0	0	0
NoReadyValidNoGrant_A	146066511	0	0	0
ReadyAndValidImplyGrant_A	146066511	846790	0	0
ReqAndReadyImplyGrant_A	146066511	846790	0	0
ReqImpliesValid_A	146066511	846790	0	0
ReqStaysHighUntilGranted0_M	146066511	0	0	0
RoundRobin_A	146066511	0	0	0
ValidKnown_A	146066511	118717830	0	0
gen_data_port_assertion.DataFlow_A	146066511	846790	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	118717830	0	0
T1	6656	6656	0	0
T3	60347	59512	0	0
T4	161896	161307	0	0
T5	36224	36224	0	0
T6	237967	236776	0	0
T7	516641	457612	0	0
T8	287706	263560	0	0
T9	211297	210147	0	0
T11	406281	315038	0	0
T12	10693	10693	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	846790	0	0
T4	161896	2157	0	0
T5	36224	0	0	0
T6	237967	1722	0	0
T7	516641	2962	0	0
T8	287706	2580	0	0
T9	211297	258	0	0
T11	406281	4436	0	0
T12	10693	0	0	0
T13	8581	0	0	0
T14	0	5597	0	0
T23	20954	0	0	0
T26	0	516	0	0
T28	0	1316	0	0
T36	0	2867	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	846790	0	0
T4	161896	2157	0	0
T5	36224	0	0	0
T6	237967	1722	0	0
T7	516641	2962	0	0
T8	287706	2580	0	0
T9	211297	258	0	0
T11	406281	4436	0	0
T12	10693	0	0	0
T13	8581	0	0	0
T14	0	5597	0	0
T23	20954	0	0	0
T26	0	516	0	0
T28	0	1316	0	0
T36	0	2867	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	118717830	0	0
T1	6656	6656	0	0
T3	60347	59512	0	0
T4	161896	161307	0	0
T5	36224	36224	0	0
T6	237967	236776	0	0
T7	516641	457612	0	0
T8	287706	263560	0	0
T9	211297	210147	0	0
T11	406281	315038	0	0
T12	10693	10693	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	118717830	0	0
T1	6656	6656	0	0
T3	60347	59512	0	0
T4	161896	161307	0	0
T5	36224	36224	0	0
T6	237967	236776	0	0
T7	516641	457612	0	0
T8	287706	263560	0	0
T9	211297	210147	0	0
T11	406281	315038	0	0
T12	10693	10693	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	846790	0	0
T4	161896	2157	0	0
T5	36224	0	0	0
T6	237967	1722	0	0
T7	516641	2962	0	0
T8	287706	2580	0	0
T9	211297	258	0	0
T11	406281	4436	0	0
T12	10693	0	0	0
T13	8581	0	0	0
T14	0	5597	0	0
T23	20954	0	0	0
T26	0	516	0	0
T28	0	1316	0	0
T36	0	2867	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	846790	0	0
T4	161896	2157	0	0
T5	36224	0	0	0
T6	237967	1722	0	0
T7	516641	2962	0	0
T8	287706	2580	0	0
T9	211297	258	0	0
T11	406281	4436	0	0
T12	10693	0	0	0
T13	8581	0	0	0
T14	0	5597	0	0
T23	20954	0	0	0
T26	0	516	0	0
T28	0	1316	0	0
T36	0	2867	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	846790	0	0
T4	161896	2157	0	0
T5	36224	0	0	0
T6	237967	1722	0	0
T7	516641	2962	0	0
T8	287706	2580	0	0
T9	211297	258	0	0
T11	406281	4436	0	0
T12	10693	0	0	0
T13	8581	0	0	0
T14	0	5597	0	0
T23	20954	0	0	0
T26	0	516	0	0
T28	0	1316	0	0
T36	0	2867	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	846790	0	0
T4	161896	2157	0	0
T5	36224	0	0	0
T6	237967	1722	0	0
T7	516641	2962	0	0
T8	287706	2580	0	0
T9	211297	258	0	0
T11	406281	4436	0	0
T12	10693	0	0	0
T13	8581	0	0	0
T14	0	5597	0	0
T23	20954	0	0	0
T26	0	516	0	0
T28	0	1316	0	0
T36	0	2867	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	118717830	0	0
T1	6656	6656	0	0
T3	60347	59512	0	0
T4	161896	161307	0	0
T5	36224	36224	0	0
T6	237967	236776	0	0
T7	516641	457612	0	0
T8	287706	263560	0	0
T9	211297	210147	0	0
T11	406281	315038	0	0
T12	10693	10693	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146066511	846790	0	0
T4	161896	2157	0	0
T5	36224	0	0	0
T6	237967	1722	0	0
T7	516641	2962	0	0
T8	287706	2580	0	0
T9	211297	258	0	0
T11	406281	4436	0	0
T12	10693	0	0	0
T13	8581	0	0	0
T14	0	5597	0	0
T23	20954	0	0	0
T26	0	516	0	0
T28	0	1316	0	0
T36	0	2867	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430056397	429966791	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	430056397	2204253	0	0
GntImpliesValid_A	430056397	2204253	0	0
GrantKnown_A	430056397	429966791	0	0
IdxKnown_A	430056397	429966791	0	0
IndexIsCorrect_A	430056397	2204253	0	0
LockArbDecision_A	430056397	0	0	0
NoReadyValidNoGrant_A	430056397	0	0	0
ReadyAndValidImplyGrant_A	430056397	2204253	0	0
ReqAndReadyImplyGrant_A	430056397	2204253	0	0
ReqImpliesValid_A	430056397	2204253	0	0
ReqStaysHighUntilGranted0_M	430056397	0	0	0
RoundRobin_A	430056397	3	0	976
ValidKnown_A	430056397	429966791	0	0
gen_data_port_assertion.DataFlow_A	430056397	2204253	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	429966791	0	0
T1	22767	22687	0	0
T2	1385	1297	0	0
T3	420577	420521	0	0
T4	104304	104206	0	0
T5	292933	292868	0	0
T6	155411	155212	0	0
T7	411975	411968	0	0
T8	146873	146864	0	0
T9	105264	105189	0	0
T10	1829	1772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	2204253	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	104304	2666	0	0
T5	292933	832	0	0
T6	155411	7633	0	0
T7	411975	8043	0	0
T8	146873	4667	0	0
T9	105264	5058	0	0
T10	1829	0	0	0
T11	0	8996	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	2204253	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	104304	2666	0	0
T5	292933	832	0	0
T6	155411	7633	0	0
T7	411975	8043	0	0
T8	146873	4667	0	0
T9	105264	5058	0	0
T10	1829	0	0	0
T11	0	8996	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	429966791	0	0
T1	22767	22687	0	0
T2	1385	1297	0	0
T3	420577	420521	0	0
T4	104304	104206	0	0
T5	292933	292868	0	0
T6	155411	155212	0	0
T7	411975	411968	0	0
T8	146873	146864	0	0
T9	105264	105189	0	0
T10	1829	1772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	429966791	0	0
T1	22767	22687	0	0
T2	1385	1297	0	0
T3	420577	420521	0	0
T4	104304	104206	0	0
T5	292933	292868	0	0
T6	155411	155212	0	0
T7	411975	411968	0	0
T8	146873	146864	0	0
T9	105264	105189	0	0
T10	1829	1772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	2204253	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	104304	2666	0	0
T5	292933	832	0	0
T6	155411	7633	0	0
T7	411975	8043	0	0
T8	146873	4667	0	0
T9	105264	5058	0	0
T10	1829	0	0	0
T11	0	8996	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	2204253	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	104304	2666	0	0
T5	292933	832	0	0
T6	155411	7633	0	0
T7	411975	8043	0	0
T8	146873	4667	0	0
T9	105264	5058	0	0
T10	1829	0	0	0
T11	0	8996	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	2204253	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	104304	2666	0	0
T5	292933	832	0	0
T6	155411	7633	0	0
T7	411975	8043	0	0
T8	146873	4667	0	0
T9	105264	5058	0	0
T10	1829	0	0	0
T11	0	8996	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	2204253	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	104304	2666	0	0
T5	292933	832	0	0
T6	155411	7633	0	0
T7	411975	8043	0	0
T8	146873	4667	0	0
T9	105264	5058	0	0
T10	1829	0	0	0
T11	0	8996	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	3	0	976
T20	5381	0	0	1
T46	566866	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	9254	0	0	1
T50	19197	0	0	1
T51	14328	0	0	1
T52	1718	0	0	1
T53	810	0	0	1
T54	209493	0	0	1
T55	48798	0	0	1
T56	213492	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	429966791	0	0
T1	22767	22687	0	0
T2	1385	1297	0	0
T3	420577	420521	0	0
T4	104304	104206	0	0
T5	292933	292868	0	0
T6	155411	155212	0	0
T7	411975	411968	0	0
T8	146873	146864	0	0
T9	105264	105189	0	0
T10	1829	1772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430056397	2204253	0	0
T1	22767	832	0	0
T2	1385	0	0	0
T3	420577	832	0	0
T4	104304	2666	0	0
T5	292933	832	0	0
T6	155411	7633	0	0
T7	411975	8043	0	0
T8	146873	4667	0	0
T9	105264	5058	0	0
T10	1829	0	0	0
T11	0	8996	0	0
T12	0	832	0	0