Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	432344881	3124	0	0
addr_swap_data_rd_A	432344881	2841	0	0
addr_swap_mask_rd_A	432344881	2883	0	0
cfg_rd_A	432344881	3308	0	0
cmd_filter_0_rd_A	432344881	6486	0	0
cmd_filter_1_rd_A	432344881	6726	0	0
cmd_filter_2_rd_A	432344881	6509	0	0
cmd_filter_3_rd_A	432344881	6827	0	0
cmd_filter_4_rd_A	432344881	5998	0	0
cmd_filter_5_rd_A	432344881	7064	0	0
cmd_filter_6_rd_A	432344881	6233	0	0
cmd_filter_7_rd_A	432344881	6772	0	0
cmd_info_0_rd_A	432344881	4211	0	0
cmd_info_10_rd_A	432344881	4376	0	0
cmd_info_11_rd_A	432344881	4231	0	0
cmd_info_12_rd_A	432344881	4579	0	0
cmd_info_13_rd_A	432344881	4756	0	0
cmd_info_14_rd_A	432344881	4558	0	0
cmd_info_15_rd_A	432344881	4441	0	0
cmd_info_16_rd_A	432344881	4286	0	0
cmd_info_17_rd_A	432344881	4280	0	0
cmd_info_18_rd_A	432344881	4720	0	0
cmd_info_19_rd_A	432344881	4544	0	0
cmd_info_1_rd_A	432344881	4348	0	0
cmd_info_20_rd_A	432344881	4840	0	0
cmd_info_21_rd_A	432344881	4219	0	0
cmd_info_22_rd_A	432344881	4498	0	0
cmd_info_23_rd_A	432344881	4834	0	0
cmd_info_2_rd_A	432344881	4266	0	0
cmd_info_3_rd_A	432344881	4104	0	0
cmd_info_4_rd_A	432344881	4625	0	0
cmd_info_5_rd_A	432344881	4661	0	0
cmd_info_6_rd_A	432344881	4622	0	0
cmd_info_7_rd_A	432344881	4501	0	0
cmd_info_8_rd_A	432344881	4479	0	0
cmd_info_9_rd_A	432344881	4684	0	0
cmd_info_en4b_rd_A	432344881	3149	0	0
cmd_info_ex4b_rd_A	432344881	3067	0	0
cmd_info_wrdi_rd_A	432344881	3004	0	0
cmd_info_wren_rd_A	432344881	3012	0	0
intercept_en_rd_A	432344881	3454	0	0
intr_enable_rd_A	432344881	4671	0	0
jedec_cc_rd_A	432344881	3038	0	0
jedec_id_rd_A	432344881	3114	0	0
mailbox_addr_rd_A	432344881	2762	0	0
payload_swap_data_rd_A	432344881	2816	0	0
payload_swap_mask_rd_A	432344881	2847	0	0
read_threshold_rd_A	432344881	2764	0	0
tpm_access_0_rd_A	432344881	3228	0	0
tpm_access_1_rd_A	432344881	3136	0	0
tpm_cfg_rd_A	432344881	3252	0	0
tpm_did_vid_rd_A	432344881	3005	0	0
tpm_int_enable_rd_A	432344881	2759	0	0
tpm_int_status_rd_A	432344881	2980	0	0
tpm_int_vector_rd_A	432344881	2858	0	0
tpm_intf_capability_rd_A	432344881	2955	0	0
tpm_rid_rd_A	432344881	2811	0	0
tpm_sts_rd_A	432344881	2828	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3124	0	0
T91	8671	145	0	0
T92	5455	5	0	0
T93	2340	3	0	0
T94	4085	99	0	0
T95	8985	200	0	0
T96	1840	39	0	0
T97	37152	1	0	0
T99	4314	3	0	0
T100	6840	249	0	0
T107	8350	10	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2841	0	0
T76	4586	12	0	0
T92	5455	7	0	0
T97	37152	33	0	0
T118	7896	13	0	0
T121	179831	458	0	0
T123	181055	454	0	0
T136	4268	3	0	0
T138	8446	17	0	0
T146	19129	24	0	0
T147	7085	13	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2883	0	0
T76	4586	5	0	0
T92	5455	13	0	0
T97	37152	40	0	0
T118	7896	14	0	0
T121	179831	457	0	0
T123	181055	438	0	0
T136	4268	6	0	0
T146	19129	41	0	0
T147	7085	30	0	0
T148	16953	31	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3308	0	0
T76	4586	17	0	0
T92	5455	15	0	0
T97	37152	95	0	0
T118	7896	18	0	0
T121	179831	478	0	0
T123	181055	468	0	0
T136	4268	4	0	0
T138	8446	33	0	0
T146	19129	74	0	0
T147	7085	15	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	6486	0	0
T76	4586	13	0	0
T92	5455	15	0	0
T97	37152	751	0	0
T118	7896	93	0	0
T121	179831	469	0	0
T123	181055	492	0	0
T136	4268	147	0	0
T138	8446	53	0	0
T146	19129	47	0	0
T147	7085	3	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	6726	0	0
T76	4586	5	0	0
T92	5455	9	0	0
T97	37152	679	0	0
T118	7896	210	0	0
T121	179831	393	0	0
T123	181055	388	0	0
T136	4268	6	0	0
T138	8446	18	0	0
T146	19129	87	0	0
T147	7085	2	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	6509	0	0
T76	4586	7	0	0
T92	5455	4	0	0
T97	37152	599	0	0
T118	7896	193	0	0
T121	179831	420	0	0
T123	181055	434	0	0
T136	4268	2	0	0
T138	8446	13	0	0
T146	19129	71	0	0
T147	7085	41	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	6827	0	0
T76	4586	6	0	0
T92	5455	5	0	0
T97	37152	826	0	0
T118	7896	88	0	0
T121	179831	471	0	0
T123	181055	480	0	0
T136	4268	6	0	0
T138	8446	15	0	0
T146	19129	42	0	0
T147	7085	22	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	5998	0	0
T76	4586	11	0	0
T92	5455	124	0	0
T97	37152	618	0	0
T118	7896	98	0	0
T121	179831	495	0	0
T123	181055	389	0	0
T136	4268	1	0	0
T138	8446	14	0	0
T146	19129	23	0	0
T147	7085	6	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	7064	0	0
T76	4586	17	0	0
T92	5455	10	0	0
T97	37152	767	0	0
T118	7896	85	0	0
T121	179831	473	0	0
T123	181055	463	0	0
T136	4268	2	0	0
T138	8446	48	0	0
T146	19129	63	0	0
T147	7085	45	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	6233	0	0
T76	4586	13	0	0
T92	5455	8	0	0
T97	37152	728	0	0
T118	7896	125	0	0
T121	179831	452	0	0
T123	181055	458	0	0
T136	4268	117	0	0
T138	8446	17	0	0
T146	19129	67	0	0
T147	7085	19	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	6772	0	0
T76	4586	14	0	0
T92	5455	122	0	0
T97	37152	645	0	0
T118	7896	2	0	0
T121	179831	437	0	0
T123	181055	478	0	0
T136	4268	131	0	0
T138	8446	8	0	0
T146	19129	78	0	0
T147	7085	12	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4211	0	0
T76	4586	21	0	0
T92	5455	52	0	0
T97	37152	228	0	0
T118	7896	51	0	0
T121	179831	430	0	0
T123	181055	476	0	0
T136	4268	1	0	0
T138	8446	27	0	0
T146	19129	28	0	0
T147	7085	11	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4376	0	0
T76	4586	18	0	0
T92	5455	68	0	0
T97	37152	225	0	0
T118	7896	90	0	0
T121	179831	423	0	0
T123	181055	448	0	0
T136	4268	43	0	0
T138	8446	29	0	0
T146	19129	32	0	0
T147	7085	36	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4231	0	0
T76	4586	14	0	0
T92	5455	60	0	0
T97	37152	338	0	0
T118	7896	4	0	0
T121	179831	410	0	0
T123	181055	476	0	0
T136	4268	5	0	0
T138	8446	51	0	0
T146	19129	81	0	0
T147	7085	17	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4579	0	0
T76	4586	6	0	0
T92	5455	37	0	0
T97	37152	193	0	0
T118	7896	35	0	0
T121	179831	476	0	0
T123	181055	440	0	0
T136	4268	46	0	0
T138	8446	35	0	0
T146	19129	81	0	0
T147	7085	50	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4756	0	0
T76	4586	12	0	0
T92	5455	57	0	0
T97	37152	309	0	0
T118	7896	49	0	0
T121	179831	474	0	0
T123	181055	488	0	0
T136	4268	54	0	0
T138	8446	11	0	0
T146	19129	84	0	0
T147	7085	38	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4558	0	0
T76	4586	12	0	0
T92	5455	68	0	0
T97	37152	213	0	0
T118	7896	53	0	0
T121	179831	414	0	0
T123	181055	435	0	0
T136	4268	43	0	0
T138	8446	32	0	0
T146	19129	43	0	0
T147	7085	26	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4441	0	0
T76	4586	19	0	0
T92	5455	59	0	0
T97	37152	311	0	0
T118	7896	30	0	0
T121	179831	449	0	0
T123	181055	498	0	0
T136	4268	1	0	0
T138	8446	44	0	0
T146	19129	71	0	0
T147	7085	10	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4286	0	0
T76	4586	7	0	0
T92	5455	45	0	0
T97	37152	273	0	0
T118	7896	10	0	0
T121	179831	401	0	0
T123	181055	427	0	0
T136	4268	30	0	0
T138	8446	3	0	0
T146	19129	39	0	0
T147	7085	33	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4280	0	0
T76	4586	10	0	0
T92	5455	6	0	0
T97	37152	178	0	0
T118	7896	61	0	0
T121	179831	464	0	0
T123	181055	509	0	0
T138	8446	23	0	0
T146	19129	29	0	0
T147	7085	18	0	0
T148	16953	100	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4720	0	0
T76	4586	9	0	0
T92	5455	38	0	0
T97	37152	143	0	0
T118	7896	136	0	0
T121	179831	426	0	0
T123	181055	446	0	0
T136	4268	68	0	0
T138	8446	42	0	0
T146	19129	33	0	0
T147	7085	30	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4544	0	0
T76	4586	4	0	0
T92	5455	49	0	0
T97	37152	189	0	0
T118	7896	37	0	0
T121	179831	480	0	0
T123	181055	454	0	0
T136	4268	4	0	0
T138	8446	8	0	0
T146	19129	65	0	0
T147	7085	12	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4348	0	0
T76	4586	5	0	0
T92	5455	61	0	0
T97	37152	139	0	0
T118	7896	12	0	0
T121	179831	480	0	0
T123	181055	473	0	0
T136	4268	62	0	0
T138	8446	11	0	0
T146	19129	13	0	0
T147	7085	5	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4840	0	0
T76	4586	11	0	0
T92	5455	15	0	0
T97	37152	304	0	0
T118	7896	75	0	0
T121	179831	457	0	0
T123	181055	451	0	0
T136	4268	2	0	0
T138	8446	18	0	0
T146	19129	76	0	0
T147	7085	2	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4219	0	0
T76	4586	5	0	0
T92	5455	36	0	0
T97	37152	259	0	0
T118	7896	90	0	0
T121	179831	484	0	0
T123	181055	475	0	0
T136	4268	1	0	0
T138	8446	5	0	0
T146	19129	37	0	0
T147	7085	8	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4498	0	0
T76	4586	13	0	0
T92	5455	43	0	0
T97	37152	344	0	0
T118	7896	61	0	0
T121	179831	471	0	0
T123	181055	454	0	0
T138	8446	17	0	0
T146	19129	114	0	0
T148	16953	56	0	0
T149	14534	64	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4834	0	0
T76	4586	2	0	0
T92	5455	10	0	0
T97	37152	482	0	0
T118	7896	147	0	0
T121	179831	403	0	0
T123	181055	482	0	0
T136	4268	52	0	0
T138	8446	52	0	0
T146	19129	38	0	0
T147	7085	35	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4266	0	0
T76	4586	11	0	0
T92	5455	3	0	0
T97	37152	235	0	0
T118	7896	50	0	0
T121	179831	426	0	0
T123	181055	443	0	0
T136	4268	2	0	0
T138	8446	5	0	0
T146	19129	36	0	0
T147	7085	14	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4104	0	0
T76	4586	12	0	0
T92	5455	4	0	0
T97	37152	140	0	0
T118	7896	34	0	0
T121	179831	455	0	0
T123	181055	468	0	0
T136	4268	2	0	0
T138	8446	29	0	0
T146	19129	112	0	0
T147	7085	23	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4625	0	0
T76	4586	3	0	0
T92	5455	11	0	0
T97	37152	227	0	0
T118	7896	71	0	0
T121	179831	435	0	0
T123	181055	373	0	0
T136	4268	44	0	0
T138	8446	28	0	0
T146	19129	82	0	0
T147	7085	23	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4661	0	0
T76	4586	7	0	0
T92	5455	48	0	0
T97	37152	357	0	0
T118	7896	54	0	0
T121	179831	456	0	0
T123	181055	488	0	0
T136	4268	7	0	0
T138	8446	21	0	0
T146	19129	59	0	0
T147	7085	35	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4622	0	0
T76	4586	9	0	0
T92	5455	11	0	0
T97	37152	304	0	0
T118	7896	89	0	0
T121	179831	518	0	0
T123	181055	428	0	0
T136	4268	6	0	0
T138	8446	32	0	0
T146	19129	80	0	0
T148	16953	85	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4501	0	0
T76	4586	8	0	0
T92	5455	49	0	0
T97	37152	315	0	0
T118	7896	47	0	0
T121	179831	383	0	0
T123	181055	433	0	0
T136	4268	1	0	0
T138	8446	30	0	0
T146	19129	53	0	0
T147	7085	2	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4479	0	0
T76	4586	10	0	0
T92	5455	55	0	0
T97	37152	290	0	0
T118	7896	44	0	0
T121	179831	447	0	0
T123	181055	477	0	0
T136	4268	9	0	0
T138	8446	19	0	0
T146	19129	82	0	0
T147	7085	45	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4684	0	0
T76	4586	9	0	0
T92	5455	37	0	0
T97	37152	256	0	0
T118	7896	8	0	0
T121	179831	502	0	0
T123	181055	448	0	0
T136	4268	43	0	0
T138	8446	39	0	0
T146	19129	61	0	0
T147	7085	12	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3149	0	0
T76	4586	18	0	0
T97	37152	59	0	0
T118	7896	15	0	0
T121	179831	495	0	0
T123	181055	430	0	0
T136	4268	8	0	0
T138	8446	24	0	0
T146	19129	47	0	0
T147	7085	4	0	0
T148	16953	23	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3067	0	0
T76	4586	5	0	0
T92	5455	9	0	0
T97	37152	46	0	0
T118	7896	4	0	0
T121	179831	415	0	0
T123	181055	454	0	0
T136	4268	5	0	0
T138	8446	13	0	0
T146	19129	86	0	0
T147	7085	14	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3004	0	0
T76	4586	8	0	0
T92	5455	6	0	0
T97	37152	51	0	0
T118	7896	13	0	0
T121	179831	434	0	0
T123	181055	430	0	0
T136	4268	3	0	0
T138	8446	25	0	0
T146	19129	98	0	0
T147	7085	12	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3012	0	0
T76	4586	6	0	0
T92	5455	8	0	0
T97	37152	76	0	0
T118	7896	15	0	0
T121	179831	343	0	0
T123	181055	456	0	0
T136	4268	6	0	0
T138	8446	14	0	0
T146	19129	65	0	0
T147	7085	34	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3454	0	0
T76	4586	18	0	0
T92	5455	16	0	0
T97	37152	121	0	0
T118	7896	9	0	0
T121	179831	474	0	0
T123	181055	478	0	0
T136	4268	9	0	0
T138	8446	3	0	0
T146	19129	35	0	0
T147	7085	46	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	4671	0	0
T6	155411	16	0	0
T7	411975	0	0	0
T8	146873	0	0	0
T9	105264	0	0	0
T10	1829	0	0	0
T11	283722	0	0	0
T12	88672	0	0	0
T13	26917	0	0	0
T14	0	7	0	0
T15	0	13	0	0
T20	0	35	0	0
T23	8595	0	0	0
T24	119274	0	0	0
T150	0	8	0	0
T151	0	60	0	0
T152	0	51	0	0
T153	0	33	0	0
T154	0	19	0	0
T155	0	36	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3038	0	0
T76	4586	14	0	0
T92	5455	8	0	0
T97	37152	58	0	0
T118	7896	12	0	0
T121	179831	413	0	0
T123	181055	471	0	0
T136	4268	2	0	0
T138	8446	42	0	0
T146	19129	86	0	0
T147	7085	14	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3114	0	0
T76	4586	21	0	0
T92	5455	13	0	0
T97	37152	47	0	0
T118	7896	29	0	0
T121	179831	429	0	0
T123	181055	496	0	0
T136	4268	3	0	0
T138	8446	47	0	0
T146	19129	46	0	0
T147	7085	7	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2762	0	0
T76	4586	12	0	0
T92	5455	13	0	0
T97	37152	45	0	0
T118	7896	9	0	0
T121	179831	458	0	0
T123	181055	432	0	0
T136	4268	1	0	0
T138	8446	6	0	0
T146	19129	34	0	0
T147	7085	12	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2816	0	0
T76	4586	15	0	0
T92	5455	8	0	0
T97	37152	29	0	0
T118	7896	8	0	0
T121	179831	402	0	0
T123	181055	433	0	0
T136	4268	4	0	0
T138	8446	4	0	0
T146	19129	36	0	0
T147	7085	24	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2847	0	0
T76	4586	4	0	0
T92	5455	9	0	0
T97	37152	48	0	0
T118	7896	4	0	0
T121	179831	463	0	0
T123	181055	429	0	0
T136	4268	4	0	0
T138	8446	16	0	0
T146	19129	29	0	0
T147	7085	22	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2764	0	0
T76	4586	9	0	0
T92	5455	4	0	0
T97	37152	48	0	0
T118	7896	6	0	0
T121	179831	475	0	0
T123	181055	406	0	0
T136	4268	4	0	0
T138	8446	6	0	0
T146	19129	33	0	0
T147	7085	3	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3228	0	0
T76	4586	12	0	0
T92	5455	10	0	0
T97	37152	71	0	0
T118	7896	19	0	0
T121	179831	411	0	0
T123	181055	515	0	0
T136	4268	3	0	0
T138	8446	12	0	0
T146	19129	65	0	0
T147	7085	5	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3136	0	0
T76	4586	7	0	0
T92	5455	8	0	0
T97	37152	31	0	0
T118	7896	10	0	0
T121	179831	452	0	0
T123	181055	526	0	0
T136	4268	3	0	0
T138	8446	25	0	0
T146	19129	128	0	0
T147	7085	50	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3252	0	0
T76	4586	4	0	0
T92	5455	6	0	0
T97	37152	98	0	0
T118	7896	2	0	0
T121	179831	446	0	0
T123	181055	444	0	0
T136	4268	1	0	0
T138	8446	3	0	0
T146	19129	101	0	0
T147	7085	33	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	3005	0	0
T76	4586	13	0	0
T92	5455	7	0	0
T97	37152	52	0	0
T118	7896	12	0	0
T121	179831	479	0	0
T123	181055	409	0	0
T136	4268	13	0	0
T138	8446	30	0	0
T146	19129	103	0	0
T147	7085	24	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2759	0	0
T76	4586	17	0	0
T92	5455	9	0	0
T97	37152	52	0	0
T118	7896	7	0	0
T121	179831	424	0	0
T123	181055	420	0	0
T138	8446	17	0	0
T146	19129	43	0	0
T147	7085	32	0	0
T148	16953	20	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2980	0	0
T76	4586	15	0	0
T92	5455	9	0	0
T97	37152	43	0	0
T118	7896	11	0	0
T121	179831	446	0	0
T123	181055	481	0	0
T136	4268	4	0	0
T138	8446	46	0	0
T146	19129	34	0	0
T147	7085	23	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2858	0	0
T76	4586	5	0	0
T92	5455	12	0	0
T97	37152	42	0	0
T118	7896	2	0	0
T121	179831	499	0	0
T123	181055	426	0	0
T136	4268	4	0	0
T138	8446	7	0	0
T146	19129	32	0	0
T148	16953	15	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2955	0	0
T76	4586	14	0	0
T92	5455	5	0	0
T97	37152	52	0	0
T118	7896	5	0	0
T121	179831	472	0	0
T123	181055	402	0	0
T136	4268	8	0	0
T138	8446	40	0	0
T146	19129	55	0	0
T147	7085	46	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2811	0	0
T76	4586	9	0	0
T92	5455	10	0	0
T97	37152	29	0	0
T118	7896	17	0	0
T121	179831	397	0	0
T123	181055	419	0	0
T136	4268	9	0	0
T138	8446	23	0	0
T146	19129	117	0	0
T147	7085	37	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432344881	2828	0	0
T76	4586	3	0	0
T92	5455	7	0	0
T97	37152	43	0	0
T118	7896	2	0	0
T121	179831	435	0	0
T123	181055	444	0	0
T138	8446	16	0	0
T146	19129	59	0	0
T147	7085	8	0	0
T148	16953	27	0	0