Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3314490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4073420

1

T1

12670

T2

894

T3

878

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4011414	1			T1	20216		T2	25		T3	2
values[0x0]	1685481	1			T1	6390		T2	472		T3	439
values[0x1]	1691015	1			T1	6519		T2	410		T3	441

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2355842	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5032068

1

T1

19042

T2

898

T3

879

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28178	1			T1	2		T3	3		T4	65
valid_sources[0x01]	29311	1			T1	154		T3	2		T4	19
valid_sources[0x02]	25871	1			T1	6		T3	2		T4	61
valid_sources[0x03]	27076	1			T1	67		T3	8		T4	19
valid_sources[0x04]	26753	1			T1	88		T3	6		T4	20
valid_sources[0x05]	28051	1			T1	94		T3	2		T4	8
valid_sources[0x06]	28434	1			T1	125		T3	6		T4	34
valid_sources[0x07]	27435	1			T1	24		T3	2		T4	82
valid_sources[0x08]	27489	1			T1	64		T3	2		T5	16
valid_sources[0x09]	32818	1			T1	129		T3	5		T4	98
valid_sources[0x0a]	30463	1			T3	6		T4	47		T5	7
valid_sources[0x0b]	30874	1			T1	41		T3	4		T4	24
valid_sources[0x0c]	31590	1			T3	4		T4	4		T5	4
valid_sources[0x0d]	27312	1			T1	98		T3	4		T4	37
valid_sources[0x0e]	28849	1			T1	26		T3	2		T4	17
valid_sources[0x0f]	30027	1			T1	211		T3	8		T5	13
valid_sources[0x10]	33474	1			T1	193		T3	5		T4	65
valid_sources[0x11]	27746	1			T3	9		T4	53		T5	17
valid_sources[0x12]	32508	1			T1	32		T3	3		T4	87
valid_sources[0x13]	27194	1			T1	259		T4	63		T5	15
valid_sources[0x14]	30067	1			T1	423		T3	3		T4	4
valid_sources[0x15]	27675	1			T3	8		T4	37		T5	11
valid_sources[0x16]	26816	1			T1	88		T3	4		T4	61
valid_sources[0x17]	29358	1			T1	52		T3	1		T4	186
valid_sources[0x18]	29084	1			T1	187		T3	4		T4	15
valid_sources[0x19]	27702	1			T1	149		T3	1		T4	71
valid_sources[0x1a]	26653	1			T1	27		T3	4		T4	2
valid_sources[0x1b]	28053	1			T1	259		T3	4		T4	141
valid_sources[0x1c]	25610	1			T1	8		T3	3		T4	15
valid_sources[0x1d]	32145	1			T1	364		T3	3		T4	12
valid_sources[0x1e]	27480	1			T1	107		T3	5		T4	81
valid_sources[0x1f]	28302	1			T1	764		T3	3		T4	2
valid_sources[0x20]	27450	1			T1	28		T3	6		T4	41
valid_sources[0x21]	29385	1			T1	42		T3	1		T4	17
valid_sources[0x22]	28938	1			T1	14		T3	1		T4	19
valid_sources[0x23]	42183	1			T1	40		T3	2		T4	37
valid_sources[0x24]	25380	1			T1	13		T3	1		T4	12
valid_sources[0x25]	25280	1			T1	14		T3	1		T4	9
valid_sources[0x26]	29321	1			T1	64		T3	3		T4	16
valid_sources[0x27]	27731	1			T1	25		T3	2		T4	89
valid_sources[0x28]	28032	1			T1	3		T2	1		T3	2
valid_sources[0x29]	30592	1			T1	123		T3	2		T4	36
valid_sources[0x2a]	28436	1			T1	118		T3	2		T4	35
valid_sources[0x2b]	27594	1			T1	45		T3	1		T4	56
valid_sources[0x2c]	26740	1			T1	326		T3	1		T4	69
valid_sources[0x2d]	28045	1			T1	27		T3	1		T4	28
valid_sources[0x2e]	25562	1			T1	40		T3	4		T4	13
valid_sources[0x2f]	29431	1			T1	60		T3	7		T4	32
valid_sources[0x30]	27427	1			T1	62		T3	1		T4	83
valid_sources[0x31]	27821	1			T1	241		T3	6		T5	9
valid_sources[0x32]	30731	1			T1	381		T3	8		T4	62
valid_sources[0x33]	28777	1			T1	23		T3	1		T4	47
valid_sources[0x34]	31496	1			T1	197		T3	2		T4	85
valid_sources[0x35]	29292	1			T1	32		T3	2		T4	54
valid_sources[0x36]	26037	1			T1	117		T3	2		T4	18
valid_sources[0x37]	27055	1			T1	85		T3	6		T4	24
valid_sources[0x38]	25086	1			T1	106		T3	2		T4	31
valid_sources[0x39]	26752	1			T1	50		T3	6		T4	38
valid_sources[0x3a]	26954	1			T1	383		T3	6		T4	37
valid_sources[0x3b]	29924	1			T1	275		T3	4		T4	23
valid_sources[0x3c]	27366	1			T1	21		T3	1		T4	38
valid_sources[0x3d]	28431	1			T1	26		T3	2		T4	32
valid_sources[0x3e]	26815	1			T1	232		T2	1		T3	7
valid_sources[0x3f]	28835	1			T1	253		T2	2		T3	4
valid_sources[0x40]	29897	1			T1	2		T3	1		T4	2
valid_sources[0x41]	25945	1			T1	48		T3	12		T4	142
valid_sources[0x42]	27933	1			T1	730		T3	5		T5	13
valid_sources[0x43]	28173	1			T1	601		T3	4		T4	11
valid_sources[0x44]	27050	1			T1	72		T3	1		T4	15
valid_sources[0x45]	31362	1			T1	3		T3	5		T4	21
valid_sources[0x46]	27778	1			T1	41		T3	6		T4	13
valid_sources[0x47]	33701	1			T1	3		T3	5		T4	147
valid_sources[0x48]	27000	1			T1	97		T3	6		T4	9
valid_sources[0x49]	31839	1			T1	18		T3	2		T4	22
valid_sources[0x4a]	26847	1			T1	50		T4	15		T5	10
valid_sources[0x4b]	27138	1			T1	228		T3	7		T4	44
valid_sources[0x4c]	28665	1			T3	6		T4	33		T5	8
valid_sources[0x4d]	25731	1			T1	160		T3	2		T4	44
valid_sources[0x4e]	28391	1			T1	8		T3	2		T4	103
valid_sources[0x4f]	27227	1			T1	88		T3	5		T4	46
valid_sources[0x50]	28644	1			T1	2		T2	1		T4	84
valid_sources[0x51]	33027	1			T1	132		T3	3		T4	48
valid_sources[0x52]	25505	1			T1	67		T3	2		T4	142
valid_sources[0x53]	32141	1			T1	568		T3	2		T4	15
valid_sources[0x54]	28977	1			T1	12		T3	3		T4	88
valid_sources[0x55]	26659	1			T1	5		T3	3		T4	71
valid_sources[0x56]	29873	1			T1	317		T3	5		T4	54
valid_sources[0x57]	27993	1			T1	298		T3	3		T4	100
valid_sources[0x58]	28527	1			T1	179		T3	4		T4	4
valid_sources[0x59]	24958	1			T1	53		T4	45		T5	8
valid_sources[0x5a]	33535	1			T1	32		T3	3		T4	19
valid_sources[0x5b]	30581	1			T1	166		T3	6		T4	94
valid_sources[0x5c]	29198	1			T1	148		T3	1		T4	59
valid_sources[0x5d]	30878	1			T1	120		T3	2		T4	8
valid_sources[0x5e]	27046	1			T1	372		T3	1		T4	38
valid_sources[0x5f]	26076	1			T1	15		T3	6		T4	44
valid_sources[0x60]	30580	1			T1	1		T3	1		T4	28
valid_sources[0x61]	27369	1			T1	120		T4	84		T5	10
valid_sources[0x62]	29279	1			T1	358		T3	2		T4	38
valid_sources[0x63]	29947	1			T1	526		T3	5		T4	34
valid_sources[0x64]	28828	1			T1	32		T3	3		T4	95
valid_sources[0x65]	32608	1			T1	125		T2	5		T3	5
valid_sources[0x66]	28587	1			T1	141		T3	1		T4	1
valid_sources[0x67]	27321	1			T1	10		T3	5		T4	14
valid_sources[0x68]	27798	1			T1	10		T3	4		T4	153
valid_sources[0x69]	27125	1			T1	19		T3	1		T4	46
valid_sources[0x6a]	30192	1			T1	56		T3	5		T4	71
valid_sources[0x6b]	27723	1			T1	4		T4	84		T5	5
valid_sources[0x6c]	26657	1			T1	7		T3	1		T4	41
valid_sources[0x6d]	28341	1			T1	131		T3	2		T4	3
valid_sources[0x6e]	26157	1			T1	11		T3	2		T4	52
valid_sources[0x6f]	26551	1			T1	490		T2	1		T3	2
valid_sources[0x70]	31069	1			T1	16		T3	4		T4	47
valid_sources[0x71]	27508	1			T1	72		T4	102		T5	13
valid_sources[0x72]	26574	1			T1	189		T3	3		T4	31
valid_sources[0x73]	34662	1			T1	316		T3	1		T4	36
valid_sources[0x74]	31416	1			T1	64		T3	9		T4	50
valid_sources[0x75]	28129	1			T1	75		T2	1		T3	2
valid_sources[0x76]	25921	1			T1	368		T3	4		T4	51
valid_sources[0x77]	26511	1			T1	46		T3	2		T4	72
valid_sources[0x78]	29367	1			T1	2		T2	636		T3	3
valid_sources[0x79]	27589	1			T1	220		T3	4		T4	66
valid_sources[0x7a]	28849	1			T1	186		T3	6		T4	91
valid_sources[0x7b]	27697	1			T1	665		T3	2		T4	39
valid_sources[0x7c]	28965	1			T1	107		T3	5		T4	35
valid_sources[0x7d]	27467	1			T1	1		T3	2		T4	44
valid_sources[0x7e]	26560	1			T1	43		T3	5		T4	85
valid_sources[0x7f]	25305	1			T1	48		T3	4		T4	32
valid_sources[0x80]	28177	1			T1	89		T3	3		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1003090

1

T1

1923

T2

15

T3

1

values[0x0]

all_enables

biggest_size

1545181

1

T1

5422

T2

470

T3

438

values[0x1]

all_enables

biggest_size

1525149

1

T1

5325

T2

409

T3

439