Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3333770

1

T1

20455

T2

13

T3

4

full_word

4072502

1

T1

12670

T2

894

T3

878

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7405832	1			T1	33125		T2	907		T3	882
auto[TlIntgErrCmd]	154	1			T101	9		T102	9		T105	13
auto[TlIntgErrData]	138	1			T101	6		T102	12		T105	9
auto[TlIntgErrBoth]	148	1			T101	5		T102	9		T105	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4012899

1

T1

20216

T2

25

T3

2

auto[1]

3393373

1

T1

12909

T2

882

T3

880

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3009496	1			T1	18293		T2	10		T3	1
auto[TlIntgErrNone]	partial	auto[1]	323877	1			T1	2162		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1003204	1			T1	1923		T2	15		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3069255	1			T1	10747		T2	879		T3	877
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T101	6		T102	5		T105	5
auto[TlIntgErrCmd]	partial	auto[1]	81	1			T101	2		T102	4		T105	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T106	1		T183	1		T184	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T101	1		T105	2		T106	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T101	3		T102	7		T105	2
auto[TlIntgErrData]	partial	auto[1]	61	1			T101	2		T102	5		T105	6
auto[TlIntgErrData]	full_word	auto[0]	9	1			T101	1		T185	1		T183	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T105	1		T185	1		T186	2
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T101	3		T102	5		T105	1
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T102	3		T105	5		T106	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T101	1		T106	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T101	1		T102	1		T105	2