Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	99.29	91.20		91.67	96.77	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.14	94.52	60.33			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.14	94.52	60.33			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	145002473	20965524	0	0
DepthKnown_A	145002473	116319194	0	0
RvalidKnown_A	145002473	116319194	0	0
WreadyKnown_A	145002473	116319194	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	145002473	20965524	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	20965524	0	0
T1	273750	14935	0	0
T2	352	0	0	0
T4	785350	153686	0	0
T5	15548	14110	0	0
T6	446	0	0	0
T7	951462	169018	0	0
T8	8892	0	0	0
T9	19230	18182	0	0
T10	76118	0	0	0
T11	559	457	0	0
T12	0	10622	0	0
T13	0	180443	0	0
T32	0	174444	0	0
T37	0	25471	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	20965524	0	0
T1	273750	14935	0	0
T2	352	0	0	0
T4	785350	153686	0	0
T5	15548	14110	0	0
T6	446	0	0	0
T7	951462	169018	0	0
T8	8892	0	0	0
T9	19230	18182	0	0
T10	76118	0	0	0
T11	559	457	0	0
T12	0	10622	0	0
T13	0	180443	0	0
T32	0	174444	0	0
T37	0	25471	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	145002473	22023064	0	0
DepthKnown_A	145002473	116319194	0	0
RvalidKnown_A	145002473	116319194	0	0
WreadyKnown_A	145002473	116319194	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	145002473	22023064	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	22023064	0	0
T1	273750	15513	0	0
T2	352	0	0	0
T4	785350	161995	0	0
T5	15548	15033	0	0
T6	446	0	0	0
T7	951462	178472	0	0
T8	8892	0	0	0
T9	19230	18950	0	0
T10	76118	0	0	0
T11	559	519	0	0
T12	0	11152	0	0
T13	0	192297	0	0
T32	0	184590	0	0
T37	0	26643	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	22023064	0	0
T1	273750	15513	0	0
T2	352	0	0	0
T4	785350	161995	0	0
T5	15548	15033	0	0
T6	446	0	0	0
T7	951462	178472	0	0
T8	8892	0	0	0
T9	19230	18950	0	0
T10	76118	0	0	0
T11	559	519	0	0
T12	0	11152	0	0
T13	0	192297	0	0
T32	0	184590	0	0
T37	0	26643	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	145002473	0	0	0
DepthKnown_A	145002473	116319194	0	0
RvalidKnown_A	145002473	116319194	0	0
WreadyKnown_A	145002473	116319194	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	145002473	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T13

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Not Covered
1	1	Covered	T1,T13,T32

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T32

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T13,T32
1	0	1	Covered	T1,T13,T32
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T32

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T32

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T32

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T32
1	0	Covered	T1,T13,T32
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T6,T13
0	0	Covered	T1,T6,T13

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T32
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	145002473	5775127	0	0
DepthKnown_A	145002473	27330906	0	0
RvalidKnown_A	145002473	27330906	0	0
WreadyKnown_A	145002473	27330906	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	145002473	5775127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	5775127	0	0
T1	273750	37994	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	46806	0	0
T15	0	28948	0	0
T30	0	7246	0	0
T32	0	16448	0	0
T35	0	579	0	0
T37	0	43262	0	0
T38	0	11666	0	0
T54	0	26382	0	0
T55	0	32484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	5775127	0	0
T1	273750	37994	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	46806	0	0
T15	0	28948	0	0
T30	0	7246	0	0
T32	0	16448	0	0
T35	0	579	0	0
T37	0	43262	0	0
T38	0	11666	0	0
T54	0	26382	0	0
T55	0	32484	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T13

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Not Covered
1	1	Covered	T1,T13,T32

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T32

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T32

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T13,T32
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T6,T13
0	0	Covered	T1,T6,T13

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T32
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	145002473	185671	0	0
DepthKnown_A	145002473	27330906	0	0
RvalidKnown_A	145002473	27330906	0	0
WreadyKnown_A	145002473	27330906	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	145002473	185671	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	185671	0	0
T1	273750	1217	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	1500	0	0
T15	0	932	0	0
T30	0	235	0	0
T32	0	531	0	0
T35	0	18	0	0
T37	0	1391	0	0
T38	0	380	0	0
T54	0	849	0	0
T55	0	1043	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	185671	0	0
T1	273750	1217	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	1500	0	0
T15	0	932	0	0
T30	0	235	0	0
T32	0	531	0	0
T35	0	18	0	0
T37	0	1391	0	0
T38	0	380	0	0
T54	0	849	0	0
T55	0	1043	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429748488	3158853	0	0
DepthKnown_A	429748488	429660153	0	0
RvalidKnown_A	429748488	429660153	0	0
WreadyKnown_A	429748488	429660153	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	429748488	3158853	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	3158853	0	0
T1	168330	3343	0	0
T2	12686	3627	0	0
T3	3142	834	0	0
T4	373887	25323	0	0
T5	50170	841	0	0
T6	3352	0	0	0
T7	674988	29038	0	0
T8	14830	832	0	0
T9	67273	2645	0	0
T10	381957	839	0	0
T11	0	833	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	3158853	0	0
T1	168330	3343	0	0
T2	12686	3627	0	0
T3	3142	834	0	0
T4	373887	25323	0	0
T5	50170	841	0	0
T6	3352	0	0	0
T7	674988	29038	0	0
T8	14830	832	0	0
T9	67273	2645	0	0
T10	381957	839	0	0
T11	0	833	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429748488	0	0	0
DepthKnown_A	429748488	429660153	0	0
RvalidKnown_A	429748488	429660153	0	0
WreadyKnown_A	429748488	429660153	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	429748488	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	0	0	0