Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431957862	2862645	0	0
DepthKnown_A	431957862	431821479	0	0
RvalidKnown_A	431957862	431821479	0	0
WreadyKnown_A	431957862	431821479	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2862645	0	0
T1	168330	6665	0	0
T2	12686	832	0	0
T3	3142	1665	0	0
T4	373887	16664	0	0
T5	50170	1672	0	0
T6	3352	0	0	0
T7	674988	18318	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	1670	0	0
T11	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431957862	3183143	0	0
DepthKnown_A	431957862	431821479	0	0
RvalidKnown_A	431957862	431821479	0	0
WreadyKnown_A	431957862	431821479	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3183143	0	0
T1	168330	3343	0	0
T2	12686	3627	0	0
T3	3142	834	0	0
T4	373887	25323	0	0
T5	50170	841	0	0
T6	3352	0	0	0
T7	674988	29038	0	0
T8	14830	832	0	0
T9	67273	2645	0	0
T10	381957	839	0	0
T11	0	833	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431957862	183746	0	0
DepthKnown_A	431957862	431821479	0	0
RvalidKnown_A	431957862	431821479	0	0
WreadyKnown_A	431957862	431821479	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	183746	0	0
T1	168330	953	0	0
T2	12686	0	0	0
T3	3142	0	0	0
T4	373887	516	0	0
T5	50170	0	0	0
T6	3352	0	0	0
T7	674988	154	0	0
T8	14830	0	0	0
T9	67273	0	0	0
T10	381957	0	0	0
T13	0	1313	0	0
T32	0	799	0	0
T35	0	30	0	0
T37	0	1359	0	0
T38	0	280	0	0
T48	0	129	0	0
T49	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431957862	416039	0	0
DepthKnown_A	431957862	431821479	0	0
RvalidKnown_A	431957862	431821479	0	0
WreadyKnown_A	431957862	431821479	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	416039	0	0
T1	168330	4293	0	0
T2	12686	0	0	0
T3	3142	0	0	0
T4	373887	2338	0	0
T5	50170	0	0	0
T6	3352	0	0	0
T7	674988	665	0	0
T8	14830	0	0	0
T9	67273	0	0	0
T10	381957	0	0	0
T13	0	6137	0	0
T32	0	799	0	0
T35	0	30	0	0
T37	0	1359	0	0
T38	0	1232	0	0
T48	0	629	0	0
T49	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431957862	5724157	0	0
DepthKnown_A	431957862	431821479	0	0
RvalidKnown_A	431957862	431821479	0	0
WreadyKnown_A	431957862	431821479	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	5724157	0	0
T1	168330	31086	0	0
T2	12686	81	0	0
T3	3142	50	0	0
T4	373887	1353	0	0
T5	50170	1838	0	0
T6	3352	14	0	0
T7	674988	10298	0	0
T8	14830	284	0	0
T9	67273	1300	0	0
T10	381957	11249	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431957862	11803962	0	0
DepthKnown_A	431957862	431821479	0	0
RvalidKnown_A	431957862	431821479	0	0
WreadyKnown_A	431957862	431821479	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	11803962	0	0
T1	168330	127673	0	0
T2	12686	373	0	0
T3	3142	245	0	0
T4	373887	5385	0	0
T5	50170	7892	0	0
T6	3352	14	0	0
T7	674988	44576	0	0
T8	14830	284	0	0
T9	67273	4273	0	0
T10	381957	49468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	431821479	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0