Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T32
1	0	Covered	T1,T13,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Unreachable
1	1	Covered	T1,T13,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	719753434	573310253	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	719753434	3650079	0	0
GntImpliesValid_A	719753434	3650079	0	0
GrantKnown_A	719753434	573310253	0	0
IdxKnown_A	719753434	573310253	0	0
IndexIsCorrect_A	719753434	3650079	0	0
LockArbDecision_A	719753434	0	0	0
NoReadyValidNoGrant_A	719753434	0	0	0
ReadyAndValidImplyGrant_A	719753434	3650079	0	0
ReqAndReadyImplyGrant_A	719753434	3650079	0	0
ReqImpliesValid_A	719753434	3650079	0	0
ReqStaysHighUntilGranted0_M	719753434	0	0	0
RoundRobin_A	719753434	4	0	974
ValidKnown_A	719753434	573310253	0	0
gen_data_port_assertion.DataFlow_A	719753434	3650079	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	573310253	0	0
T1	715830	433153	0	0
T2	13390	12987	0	0
T3	3142	3077	0	0
T4	1944587	1157626	0	0
T5	81266	65451	0	0
T6	4244	3555	0	0
T7	2577912	1624927	0	0
T8	32614	23428	0	0
T9	105733	86452	0	0
T10	534193	457525	0	0
T11	1118	559	0	0
T12	0	44354	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	3650079	0	0
T1	715830	11377	0	0
T2	13390	832	0	0
T3	3142	832	0	0
T4	1944587	18573	0	0
T5	81266	832	0	0
T6	4244	0	0	0
T7	2577912	12453	0	0
T8	32614	832	0	0
T9	105733	832	0	0
T10	534193	832	0	0
T11	1118	832	0	0
T13	0	11529	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	7215	0	0
T35	0	140	0	0
T37	0	7800	0	0
T38	0	3771	0	0
T48	0	2841	0	0
T49	0	7	0	0
T54	0	1881	0	0
T55	0	3734	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	3650079	0	0
T1	715830	11377	0	0
T2	13390	832	0	0
T3	3142	832	0	0
T4	1944587	18573	0	0
T5	81266	832	0	0
T6	4244	0	0	0
T7	2577912	12453	0	0
T8	32614	832	0	0
T9	105733	832	0	0
T10	534193	832	0	0
T11	1118	832	0	0
T13	0	11529	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	7215	0	0
T35	0	140	0	0
T37	0	7800	0	0
T38	0	3771	0	0
T48	0	2841	0	0
T49	0	7	0	0
T54	0	1881	0	0
T55	0	3734	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	573310253	0	0
T1	715830	433153	0	0
T2	13390	12987	0	0
T3	3142	3077	0	0
T4	1944587	1157626	0	0
T5	81266	65451	0	0
T6	4244	3555	0	0
T7	2577912	1624927	0	0
T8	32614	23428	0	0
T9	105733	86452	0	0
T10	534193	457525	0	0
T11	1118	559	0	0
T12	0	44354	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	573310253	0	0
T1	715830	433153	0	0
T2	13390	12987	0	0
T3	3142	3077	0	0
T4	1944587	1157626	0	0
T5	81266	65451	0	0
T6	4244	3555	0	0
T7	2577912	1624927	0	0
T8	32614	23428	0	0
T9	105733	86452	0	0
T10	534193	457525	0	0
T11	1118	559	0	0
T12	0	44354	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	3650079	0	0
T1	715830	11377	0	0
T2	13390	832	0	0
T3	3142	832	0	0
T4	1944587	18573	0	0
T5	81266	832	0	0
T6	4244	0	0	0
T7	2577912	12453	0	0
T8	32614	832	0	0
T9	105733	832	0	0
T10	534193	832	0	0
T11	1118	832	0	0
T13	0	11529	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	7215	0	0
T35	0	140	0	0
T37	0	7800	0	0
T38	0	3771	0	0
T48	0	2841	0	0
T49	0	7	0	0
T54	0	1881	0	0
T55	0	3734	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	3650079	0	0
T1	715830	11377	0	0
T2	13390	832	0	0
T3	3142	832	0	0
T4	1944587	18573	0	0
T5	81266	832	0	0
T6	4244	0	0	0
T7	2577912	12453	0	0
T8	32614	832	0	0
T9	105733	832	0	0
T10	534193	832	0	0
T11	1118	832	0	0
T13	0	11529	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	7215	0	0
T35	0	140	0	0
T37	0	7800	0	0
T38	0	3771	0	0
T48	0	2841	0	0
T49	0	7	0	0
T54	0	1881	0	0
T55	0	3734	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	3650079	0	0
T1	715830	11377	0	0
T2	13390	832	0	0
T3	3142	832	0	0
T4	1944587	18573	0	0
T5	81266	832	0	0
T6	4244	0	0	0
T7	2577912	12453	0	0
T8	32614	832	0	0
T9	105733	832	0	0
T10	534193	832	0	0
T11	1118	832	0	0
T13	0	11529	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	7215	0	0
T35	0	140	0	0
T37	0	7800	0	0
T38	0	3771	0	0
T48	0	2841	0	0
T49	0	7	0	0
T54	0	1881	0	0
T55	0	3734	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	3650079	0	0
T1	715830	11377	0	0
T2	13390	832	0	0
T3	3142	832	0	0
T4	1944587	18573	0	0
T5	81266	832	0	0
T6	4244	0	0	0
T7	2577912	12453	0	0
T8	32614	832	0	0
T9	105733	832	0	0
T10	534193	832	0	0
T11	1118	832	0	0
T13	0	11529	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	7215	0	0
T35	0	140	0	0
T37	0	7800	0	0
T38	0	3771	0	0
T48	0	2841	0	0
T49	0	7	0	0
T54	0	1881	0	0
T55	0	3734	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	4	0	974
T56	191044	2	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	151181	0	0	1
T60	2116	0	0	1
T61	503750	0	0	1
T62	8041	0	0	1
T63	442808	0	0	1
T64	46245	0	0	1
T65	41668	0	0	1
T66	1347	0	0	1
T67	1245	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	573310253	0	0
T1	715830	433153	0	0
T2	13390	12987	0	0
T3	3142	3077	0	0
T4	1944587	1157626	0	0
T5	81266	65451	0	0
T6	4244	3555	0	0
T7	2577912	1624927	0	0
T8	32614	23428	0	0
T9	105733	86452	0	0
T10	534193	457525	0	0
T11	1118	559	0	0
T12	0	44354	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719753434	3650079	0	0
T1	715830	11377	0	0
T2	13390	832	0	0
T3	3142	832	0	0
T4	1944587	18573	0	0
T5	81266	832	0	0
T6	4244	0	0	0
T7	2577912	12453	0	0
T8	32614	832	0	0
T9	105733	832	0	0
T10	534193	832	0	0
T11	1118	832	0	0
T13	0	11529	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	7215	0	0
T35	0	140	0	0
T37	0	7800	0	0
T38	0	3771	0	0
T48	0	2841	0	0
T49	0	7	0	0
T54	0	1881	0	0
T55	0	3734	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T32
1	0	Covered	T1,T13,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Unreachable
1	1	Covered	T1,T13,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T13,T32
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145002473	27330906	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	145002473	610166	0	0
GntImpliesValid_A	145002473	610166	0	0
GrantKnown_A	145002473	27330906	0	0
IdxKnown_A	145002473	27330906	0	0
IndexIsCorrect_A	145002473	610166	0	0
LockArbDecision_A	145002473	0	0	0
NoReadyValidNoGrant_A	145002473	0	0	0
ReadyAndValidImplyGrant_A	145002473	610166	0	0
ReqAndReadyImplyGrant_A	145002473	610166	0	0
ReqImpliesValid_A	145002473	610166	0	0
ReqStaysHighUntilGranted0_M	145002473	0	0	0
RoundRobin_A	145002473	0	0	0
ValidKnown_A	145002473	27330906	0	0
gen_data_port_assertion.DataFlow_A	145002473	610166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	610166	0	0
T1	273750	4414	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	4585	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	2063	0	0
T35	0	140	0	0
T37	0	5175	0	0
T38	0	991	0	0
T54	0	1881	0	0
T55	0	3734	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	610166	0	0
T1	273750	4414	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	4585	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	2063	0	0
T35	0	140	0	0
T37	0	5175	0	0
T38	0	991	0	0
T54	0	1881	0	0
T55	0	3734	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	610166	0	0
T1	273750	4414	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	4585	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	2063	0	0
T35	0	140	0	0
T37	0	5175	0	0
T38	0	991	0	0
T54	0	1881	0	0
T55	0	3734	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	610166	0	0
T1	273750	4414	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	4585	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	2063	0	0
T35	0	140	0	0
T37	0	5175	0	0
T38	0	991	0	0
T54	0	1881	0	0
T55	0	3734	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	610166	0	0
T1	273750	4414	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	4585	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	2063	0	0
T35	0	140	0	0
T37	0	5175	0	0
T38	0	991	0	0
T54	0	1881	0	0
T55	0	3734	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	610166	0	0
T1	273750	4414	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	4585	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	2063	0	0
T35	0	140	0	0
T37	0	5175	0	0
T38	0	991	0	0
T54	0	1881	0	0
T55	0	3734	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	27330906	0	0
T1	273750	106576	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	288	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	544016	0	0
T31	0	720	0	0
T32	0	43608	0	0
T33	0	576	0	0
T34	0	97584	0	0
T35	0	1928	0	0
T37	0	126336	0	0
T38	0	76264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	610166	0	0
T1	273750	4414	0	0
T2	352	0	0	0
T4	785350	0	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	0	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	4585	0	0
T15	0	3734	0	0
T30	0	631	0	0
T32	0	2063	0	0
T35	0	140	0	0
T37	0	5175	0	0
T38	0	991	0	0
T54	0	1881	0	0
T55	0	3734	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145002473	116319194	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	145002473	794046	0	0
GntImpliesValid_A	145002473	794046	0	0
GrantKnown_A	145002473	116319194	0	0
IdxKnown_A	145002473	116319194	0	0
IndexIsCorrect_A	145002473	794046	0	0
LockArbDecision_A	145002473	0	0	0
NoReadyValidNoGrant_A	145002473	0	0	0
ReadyAndValidImplyGrant_A	145002473	794046	0	0
ReqAndReadyImplyGrant_A	145002473	794046	0	0
ReqImpliesValid_A	145002473	794046	0	0
ReqStaysHighUntilGranted0_M	145002473	0	0	0
RoundRobin_A	145002473	0	0	0
ValidKnown_A	145002473	116319194	0	0
gen_data_port_assertion.DataFlow_A	145002473	794046	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	794046	0	0
T1	273750	1456	0	0
T2	352	0	0	0
T4	785350	7218	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	637	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	6944	0	0
T32	0	5152	0	0
T37	0	2625	0	0
T38	0	2780	0	0
T48	0	2841	0	0
T49	0	7	0	0
T68	0	1164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	794046	0	0
T1	273750	1456	0	0
T2	352	0	0	0
T4	785350	7218	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	637	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	6944	0	0
T32	0	5152	0	0
T37	0	2625	0	0
T38	0	2780	0	0
T48	0	2841	0	0
T49	0	7	0	0
T68	0	1164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	794046	0	0
T1	273750	1456	0	0
T2	352	0	0	0
T4	785350	7218	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	637	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	6944	0	0
T32	0	5152	0	0
T37	0	2625	0	0
T38	0	2780	0	0
T48	0	2841	0	0
T49	0	7	0	0
T68	0	1164	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	794046	0	0
T1	273750	1456	0	0
T2	352	0	0	0
T4	785350	7218	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	637	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	6944	0	0
T32	0	5152	0	0
T37	0	2625	0	0
T38	0	2780	0	0
T48	0	2841	0	0
T49	0	7	0	0
T68	0	1164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	794046	0	0
T1	273750	1456	0	0
T2	352	0	0	0
T4	785350	7218	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	637	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	6944	0	0
T32	0	5152	0	0
T37	0	2625	0	0
T38	0	2780	0	0
T48	0	2841	0	0
T49	0	7	0	0
T68	0	1164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	794046	0	0
T1	273750	1456	0	0
T2	352	0	0	0
T4	785350	7218	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	637	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	6944	0	0
T32	0	5152	0	0
T37	0	2625	0	0
T38	0	2780	0	0
T48	0	2841	0	0
T49	0	7	0	0
T68	0	1164	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	116319194	0	0
T1	273750	158252	0	0
T2	352	352	0	0
T4	785350	783818	0	0
T5	15548	15345	0	0
T6	446	0	0	0
T7	951462	949944	0	0
T8	8892	8656	0	0
T9	19230	19230	0	0
T10	76118	75632	0	0
T11	559	559	0	0
T12	0	44354	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145002473	794046	0	0
T1	273750	1456	0	0
T2	352	0	0	0
T4	785350	7218	0	0
T5	15548	0	0	0
T6	446	0	0	0
T7	951462	637	0	0
T8	8892	0	0	0
T9	19230	0	0	0
T10	76118	0	0	0
T11	559	0	0	0
T13	0	6944	0	0
T32	0	5152	0	0
T37	0	2625	0	0
T38	0	2780	0	0
T48	0	2841	0	0
T49	0	7	0	0
T68	0	1164	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429748488	429660153	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	429748488	2245867	0	0
GntImpliesValid_A	429748488	2245867	0	0
GrantKnown_A	429748488	429660153	0	0
IdxKnown_A	429748488	429660153	0	0
IndexIsCorrect_A	429748488	2245867	0	0
LockArbDecision_A	429748488	0	0	0
NoReadyValidNoGrant_A	429748488	0	0	0
ReadyAndValidImplyGrant_A	429748488	2245867	0	0
ReqAndReadyImplyGrant_A	429748488	2245867	0	0
ReqImpliesValid_A	429748488	2245867	0	0
ReqStaysHighUntilGranted0_M	429748488	0	0	0
RoundRobin_A	429748488	4	0	974
ValidKnown_A	429748488	429660153	0	0
gen_data_port_assertion.DataFlow_A	429748488	2245867	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	2245867	0	0
T1	168330	5507	0	0
T2	12686	832	0	0
T3	3142	832	0	0
T4	373887	11355	0	0
T5	50170	832	0	0
T6	3352	0	0	0
T7	674988	11816	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	832	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	2245867	0	0
T1	168330	5507	0	0
T2	12686	832	0	0
T3	3142	832	0	0
T4	373887	11355	0	0
T5	50170	832	0	0
T6	3352	0	0	0
T7	674988	11816	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	832	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	2245867	0	0
T1	168330	5507	0	0
T2	12686	832	0	0
T3	3142	832	0	0
T4	373887	11355	0	0
T5	50170	832	0	0
T6	3352	0	0	0
T7	674988	11816	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	832	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	2245867	0	0
T1	168330	5507	0	0
T2	12686	832	0	0
T3	3142	832	0	0
T4	373887	11355	0	0
T5	50170	832	0	0
T6	3352	0	0	0
T7	674988	11816	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	832	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	2245867	0	0
T1	168330	5507	0	0
T2	12686	832	0	0
T3	3142	832	0	0
T4	373887	11355	0	0
T5	50170	832	0	0
T6	3352	0	0	0
T7	674988	11816	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	832	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	2245867	0	0
T1	168330	5507	0	0
T2	12686	832	0	0
T3	3142	832	0	0
T4	373887	11355	0	0
T5	50170	832	0	0
T6	3352	0	0	0
T7	674988	11816	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	832	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	4	0	974
T56	191044	2	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	151181	0	0	1
T60	2116	0	0	1
T61	503750	0	0	1
T62	8041	0	0	1
T63	442808	0	0	1
T64	46245	0	0	1
T65	41668	0	0	1
T66	1347	0	0	1
T67	1245	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	429660153	0	0
T1	168330	168325	0	0
T2	12686	12635	0	0
T3	3142	3077	0	0
T4	373887	373808	0	0
T5	50170	50106	0	0
T6	3352	3267	0	0
T7	674988	674983	0	0
T8	14830	14772	0	0
T9	67273	67222	0	0
T10	381957	381893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429748488	2245867	0	0
T1	168330	5507	0	0
T2	12686	832	0	0
T3	3142	832	0	0
T4	373887	11355	0	0
T5	50170	832	0	0
T6	3352	0	0	0
T7	674988	11816	0	0
T8	14830	832	0	0
T9	67273	832	0	0
T10	381957	832	0	0
T11	0	832	0	0