Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	431957862	3865	0	0
addr_swap_data_rd_A	431957862	1448	0	0
addr_swap_mask_rd_A	431957862	1447	0	0
cfg_rd_A	431957862	1625	0	0
cmd_filter_0_rd_A	431957862	5426	0	0
cmd_filter_1_rd_A	431957862	5815	0	0
cmd_filter_2_rd_A	431957862	6220	0	0
cmd_filter_3_rd_A	431957862	6972	0	0
cmd_filter_4_rd_A	431957862	5607	0	0
cmd_filter_5_rd_A	431957862	5347	0	0
cmd_filter_6_rd_A	431957862	6454	0	0
cmd_filter_7_rd_A	431957862	5525	0	0
cmd_info_0_rd_A	431957862	3194	0	0
cmd_info_10_rd_A	431957862	3183	0	0
cmd_info_11_rd_A	431957862	3222	0	0
cmd_info_12_rd_A	431957862	3385	0	0
cmd_info_13_rd_A	431957862	3193	0	0
cmd_info_14_rd_A	431957862	3065	0	0
cmd_info_15_rd_A	431957862	2878	0	0
cmd_info_16_rd_A	431957862	3151	0	0
cmd_info_17_rd_A	431957862	3094	0	0
cmd_info_18_rd_A	431957862	3185	0	0
cmd_info_19_rd_A	431957862	2917	0	0
cmd_info_1_rd_A	431957862	3017	0	0
cmd_info_20_rd_A	431957862	2596	0	0
cmd_info_21_rd_A	431957862	3137	0	0
cmd_info_22_rd_A	431957862	3011	0	0
cmd_info_23_rd_A	431957862	2951	0	0
cmd_info_2_rd_A	431957862	2964	0	0
cmd_info_3_rd_A	431957862	3099	0	0
cmd_info_4_rd_A	431957862	2943	0	0
cmd_info_5_rd_A	431957862	3198	0	0
cmd_info_6_rd_A	431957862	2999	0	0
cmd_info_7_rd_A	431957862	3479	0	0
cmd_info_8_rd_A	431957862	3012	0	0
cmd_info_9_rd_A	431957862	3166	0	0
cmd_info_en4b_rd_A	431957862	1613	0	0
cmd_info_ex4b_rd_A	431957862	1574	0	0
cmd_info_wrdi_rd_A	431957862	1620	0	0
cmd_info_wren_rd_A	431957862	1617	0	0
intercept_en_rd_A	431957862	1907	0	0
intr_enable_rd_A	431957862	2910	0	0
jedec_cc_rd_A	431957862	1628	0	0
jedec_id_rd_A	431957862	1488	0	0
mailbox_addr_rd_A	431957862	1433	0	0
payload_swap_data_rd_A	431957862	1447	0	0
payload_swap_mask_rd_A	431957862	1493	0	0
read_threshold_rd_A	431957862	1481	0	0
tpm_access_0_rd_A	431957862	1783	0	0
tpm_access_1_rd_A	431957862	1391	0	0
tpm_cfg_rd_A	431957862	2111	0	0
tpm_did_vid_rd_A	431957862	1647	0	0
tpm_int_enable_rd_A	431957862	1492	0	0
tpm_int_status_rd_A	431957862	1508	0	0
tpm_int_vector_rd_A	431957862	1452	0	0
tpm_intf_capability_rd_A	431957862	1470	0	0
tpm_rid_rd_A	431957862	1528	0	0
tpm_sts_rd_A	431957862	1453	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3865	0	0
T102	78226	3	0	0
T103	3208	68	0	0
T104	8443	10	0	0
T105	80223	4	0	0
T106	85749	9	0	0
T107	15903	361	0	0
T108	15503	6	0	0
T127	9651	14	0	0
T128	11187	3	0	0
T129	29648	6	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1448	0	0
T86	3133	6	0	0
T108	15503	25	0	0
T128	11187	21	0	0
T130	5818	9	0	0
T132	4077	6	0	0
T133	8478	14	0	0
T156	7906	9	0	0
T157	14424	30	0	0
T158	7272	20	0	0
T159	4492	6	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1447	0	0
T86	3133	4	0	0
T108	15503	14	0	0
T128	11187	4	0	0
T130	5818	8	0	0
T132	4077	1	0	0
T133	8478	7	0	0
T156	7906	15	0	0
T157	14424	33	0	0
T158	7272	16	0	0
T159	4492	6	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1625	0	0
T86	3133	7	0	0
T108	15503	41	0	0
T112	12611	5	0	0
T128	11187	40	0	0
T130	5818	8	0	0
T132	4077	3	0	0
T133	8478	21	0	0
T156	7906	12	0	0
T157	14424	67	0	0
T159	4492	21	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	5426	0	0
T86	3133	8	0	0
T108	15503	239	0	0
T128	11187	14	0	0
T130	5818	101	0	0
T133	8478	152	0	0
T156	7906	5	0	0
T157	14424	42	0	0
T158	7272	62	0	0
T159	4492	133	0	0
T160	13831	58	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	5815	0	0
T86	3133	6	0	0
T108	15503	123	0	0
T128	11187	128	0	0
T130	5818	17	0	0
T132	4077	118	0	0
T133	8478	145	0	0
T156	7906	144	0	0
T157	14424	20	0	0
T158	7272	4	0	0
T159	4492	3	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	6220	0	0
T86	3133	7	0	0
T108	15503	299	0	0
T128	11187	119	0	0
T130	5818	96	0	0
T133	8478	253	0	0
T156	7906	142	0	0
T157	14424	72	0	0
T158	7272	23	0	0
T159	4492	2	0	0
T160	13831	55	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	6972	0	0
T86	3133	10	0	0
T108	15503	433	0	0
T128	11187	162	0	0
T130	5818	98	0	0
T132	4077	2	0	0
T133	8478	214	0	0
T156	7906	270	0	0
T157	14424	48	0	0
T158	7272	54	0	0
T159	4492	135	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	5607	0	0
T86	3133	9	0	0
T108	15503	26	0	0
T128	11187	252	0	0
T130	5818	93	0	0
T132	4077	123	0	0
T133	8478	261	0	0
T156	7906	111	0	0
T157	14424	45	0	0
T158	7272	43	0	0
T159	4492	8	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	5347	0	0
T86	3133	6	0	0
T108	15503	428	0	0
T128	11187	142	0	0
T130	5818	8	0	0
T132	4077	2	0	0
T133	8478	8	0	0
T156	7906	88	0	0
T157	14424	76	0	0
T158	7272	12	0	0
T159	4492	4	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	6454	0	0
T86	3133	4	0	0
T108	15503	135	0	0
T128	11187	17	0	0
T130	5818	103	0	0
T132	4077	110	0	0
T133	8478	261	0	0
T156	7906	127	0	0
T157	14424	28	0	0
T158	7272	31	0	0
T159	4492	142	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	5525	0	0
T86	3133	10	0	0
T108	15503	18	0	0
T128	11187	137	0	0
T130	5818	147	0	0
T132	4077	3	0	0
T133	8478	5	0	0
T156	7906	239	0	0
T157	14424	57	0	0
T158	7272	42	0	0
T159	4492	122	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3194	0	0
T86	3133	13	0	0
T108	15503	84	0	0
T128	11187	10	0	0
T130	5818	3	0	0
T132	4077	4	0	0
T133	8478	43	0	0
T156	7906	57	0	0
T157	14424	35	0	0
T158	7272	4	0	0
T159	4492	58	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3183	0	0
T86	3133	4	0	0
T108	15503	133	0	0
T128	11187	100	0	0
T130	5818	6	0	0
T132	4077	74	0	0
T133	8478	10	0	0
T156	7906	104	0	0
T157	14424	30	0	0
T158	7272	10	0	0
T159	4492	49	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3222	0	0
T86	3133	11	0	0
T108	15503	61	0	0
T128	11187	111	0	0
T130	5818	1	0	0
T132	4077	53	0	0
T133	8478	58	0	0
T156	7906	66	0	0
T157	14424	47	0	0
T158	7272	23	0	0
T159	4492	51	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3385	0	0
T86	3133	2	0	0
T108	15503	62	0	0
T128	11187	113	0	0
T130	5818	54	0	0
T132	4077	49	0	0
T133	8478	41	0	0
T156	7906	98	0	0
T157	14424	85	0	0
T158	7272	13	0	0
T160	13831	45	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3193	0	0
T86	3133	7	0	0
T108	15503	92	0	0
T128	11187	63	0	0
T130	5818	11	0	0
T132	4077	57	0	0
T133	8478	76	0	0
T156	7906	99	0	0
T157	14424	52	0	0
T158	7272	4	0	0
T159	4492	61	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3065	0	0
T86	3133	7	0	0
T108	15503	49	0	0
T128	11187	70	0	0
T130	5818	36	0	0
T132	4077	46	0	0
T133	8478	89	0	0
T156	7906	5	0	0
T157	14424	106	0	0
T158	7272	21	0	0
T159	4492	7	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2878	0	0
T86	3133	7	0	0
T108	15503	113	0	0
T112	12611	1	0	0
T128	11187	62	0	0
T130	5818	2	0	0
T132	4077	46	0	0
T133	8478	4	0	0
T156	7906	3	0	0
T157	14424	27	0	0
T158	7272	48	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3151	0	0
T86	3133	11	0	0
T108	15503	117	0	0
T128	11187	126	0	0
T130	5818	4	0	0
T132	4077	43	0	0
T133	8478	99	0	0
T156	7906	37	0	0
T157	14424	64	0	0
T158	7272	47	0	0
T160	13831	32	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3094	0	0
T86	3133	6	0	0
T108	15503	141	0	0
T128	11187	11	0	0
T130	5818	8	0	0
T132	4077	22	0	0
T133	8478	3	0	0
T156	7906	36	0	0
T157	14424	24	0	0
T158	7272	28	0	0
T159	4492	3	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3185	0	0
T86	3133	7	0	0
T108	15503	66	0	0
T128	11187	139	0	0
T130	5818	3	0	0
T133	8478	13	0	0
T156	7906	80	0	0
T157	14424	58	0	0
T158	7272	12	0	0
T159	4492	52	0	0
T160	13831	39	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2917	0	0
T86	3133	9	0	0
T108	15503	136	0	0
T128	11187	16	0	0
T130	5818	7	0	0
T132	4077	43	0	0
T133	8478	2	0	0
T156	7906	62	0	0
T157	14424	28	0	0
T158	7272	25	0	0
T160	13831	53	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3017	0	0
T86	3133	16	0	0
T108	15503	75	0	0
T128	11187	57	0	0
T130	5818	6	0	0
T132	4077	58	0	0
T133	8478	44	0	0
T156	7906	104	0	0
T157	14424	69	0	0
T158	7272	17	0	0
T159	4492	9	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2596	0	0
T86	3133	7	0	0
T108	15503	24	0	0
T128	11187	8	0	0
T130	5818	9	0	0
T132	4077	63	0	0
T133	8478	63	0	0
T156	7906	3	0	0
T157	14424	86	0	0
T159	4492	2	0	0
T160	13831	31	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3137	0	0
T86	3133	9	0	0
T108	15503	109	0	0
T128	11187	21	0	0
T130	5818	36	0	0
T132	4077	2	0	0
T133	8478	76	0	0
T156	7906	60	0	0
T157	14424	24	0	0
T158	7272	10	0	0
T159	4492	44	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3011	0	0
T86	3133	11	0	0
T108	15503	43	0	0
T128	11187	50	0	0
T130	5818	6	0	0
T132	4077	59	0	0
T133	8478	60	0	0
T156	7906	102	0	0
T157	14424	58	0	0
T159	4492	53	0	0
T160	13831	30	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2951	0	0
T86	3133	8	0	0
T108	15503	89	0	0
T128	11187	116	0	0
T130	5818	61	0	0
T133	8478	57	0	0
T156	7906	61	0	0
T157	14424	26	0	0
T158	7272	21	0	0
T159	4492	61	0	0
T160	13831	18	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2964	0	0
T86	3133	1	0	0
T108	15503	159	0	0
T128	11187	17	0	0
T130	5818	49	0	0
T132	4077	55	0	0
T133	8478	61	0	0
T156	7906	50	0	0
T157	14424	51	0	0
T158	7272	20	0	0
T159	4492	41	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3099	0	0
T86	3133	1	0	0
T108	15503	142	0	0
T128	11187	44	0	0
T130	5818	46	0	0
T132	4077	39	0	0
T133	8478	92	0	0
T156	7906	119	0	0
T157	14424	49	0	0
T158	7272	15	0	0
T159	4492	6	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2943	0	0
T86	3133	5	0	0
T108	15503	116	0	0
T112	12611	9	0	0
T128	11187	24	0	0
T130	5818	12	0	0
T132	4077	29	0	0
T133	8478	48	0	0
T156	7906	68	0	0
T157	14424	45	0	0
T158	7272	27	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3198	0	0
T86	3133	9	0	0
T108	15503	157	0	0
T128	11187	38	0	0
T130	5818	50	0	0
T132	4077	9	0	0
T133	8478	51	0	0
T156	7906	67	0	0
T157	14424	35	0	0
T158	7272	30	0	0
T159	4492	3	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2999	0	0
T86	3133	1	0	0
T108	15503	103	0	0
T128	11187	128	0	0
T130	5818	7	0	0
T132	4077	3	0	0
T133	8478	67	0	0
T156	7906	3	0	0
T157	14424	43	0	0
T158	7272	8	0	0
T159	4492	62	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3479	0	0
T86	3133	8	0	0
T108	15503	95	0	0
T128	11187	112	0	0
T130	5818	47	0	0
T132	4077	2	0	0
T133	8478	58	0	0
T156	7906	66	0	0
T157	14424	31	0	0
T158	7272	13	0	0
T159	4492	63	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3012	0	0
T86	3133	13	0	0
T108	15503	67	0	0
T128	11187	69	0	0
T130	5818	61	0	0
T132	4077	8	0	0
T133	8478	12	0	0
T156	7906	13	0	0
T157	14424	63	0	0
T158	7272	9	0	0
T159	4492	4	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	3166	0	0
T86	3133	3	0	0
T108	15503	132	0	0
T128	11187	75	0	0
T130	5818	8	0	0
T132	4077	1	0	0
T133	8478	46	0	0
T156	7906	104	0	0
T157	14424	64	0	0
T158	7272	25	0	0
T159	4492	6	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1613	0	0
T86	3133	6	0	0
T108	15503	22	0	0
T128	11187	15	0	0
T130	5818	8	0	0
T132	4077	4	0	0
T133	8478	25	0	0
T156	7906	17	0	0
T157	14424	30	0	0
T158	7272	48	0	0
T159	4492	5	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1574	0	0
T86	3133	9	0	0
T108	15503	47	0	0
T112	12611	4	0	0
T128	11187	19	0	0
T130	5818	15	0	0
T132	4077	7	0	0
T133	8478	11	0	0
T156	7906	9	0	0
T157	14424	27	0	0
T158	7272	19	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1620	0	0
T86	3133	5	0	0
T108	15503	35	0	0
T128	11187	10	0	0
T130	5818	9	0	0
T132	4077	6	0	0
T133	8478	14	0	0
T156	7906	15	0	0
T157	14424	44	0	0
T158	7272	29	0	0
T159	4492	9	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1617	0	0
T86	3133	13	0	0
T108	15503	33	0	0
T112	12611	6	0	0
T128	11187	15	0	0
T130	5818	13	0	0
T132	4077	8	0	0
T133	8478	11	0	0
T156	7906	7	0	0
T157	14424	25	0	0
T158	7272	14	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1907	0	0
T86	3133	6	0	0
T108	15503	27	0	0
T128	11187	45	0	0
T130	5818	14	0	0
T132	4077	8	0	0
T133	8478	33	0	0
T156	7906	7	0	0
T157	14424	46	0	0
T158	7272	7	0	0
T159	4492	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2910	0	0
T57	270283	23	0	0
T161	0	9	0	0
T162	0	39	0	0
T163	0	26	0	0
T164	0	13	0	0
T165	0	28	0	0
T166	0	65	0	0
T167	0	9	0	0
T168	0	24	0	0
T169	0	34	0	0
T170	178691	0	0	0
T171	291768	0	0	0
T172	91561	0	0	0
T173	147025	0	0	0
T174	28530	0	0	0
T175	3031	0	0	0
T176	11213	0	0	0
T177	301753	0	0	0
T178	209918	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1628	0	0
T86	3133	6	0	0
T108	15503	21	0	0
T128	11187	17	0	0
T130	5818	10	0	0
T132	4077	6	0	0
T133	8478	7	0	0
T156	7906	22	0	0
T157	14424	49	0	0
T158	7272	29	0	0
T159	4492	7	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1488	0	0
T86	3133	8	0	0
T108	15503	54	0	0
T128	11187	19	0	0
T130	5818	12	0	0
T132	4077	3	0	0
T133	8478	14	0	0
T156	7906	2	0	0
T157	14424	37	0	0
T158	7272	4	0	0
T159	4492	2	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1433	0	0
T86	3133	4	0	0
T108	15503	28	0	0
T128	11187	20	0	0
T130	5818	13	0	0
T132	4077	1	0	0
T133	8478	6	0	0
T156	7906	1	0	0
T157	14424	39	0	0
T158	7272	1	0	0
T159	4492	9	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1447	0	0
T86	3133	9	0	0
T108	15503	30	0	0
T128	11187	4	0	0
T130	5818	13	0	0
T133	8478	7	0	0
T156	7906	5	0	0
T157	14424	37	0	0
T158	7272	20	0	0
T159	4492	8	0	0
T160	13831	79	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1493	0	0
T86	3133	2	0	0
T108	15503	25	0	0
T128	11187	15	0	0
T130	5818	4	0	0
T132	4077	5	0	0
T133	8478	14	0	0
T156	7906	18	0	0
T157	14424	54	0	0
T158	7272	30	0	0
T159	4492	7	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1481	0	0
T86	3133	9	0	0
T108	15503	17	0	0
T128	11187	27	0	0
T130	5818	10	0	0
T132	4077	1	0	0
T156	7906	5	0	0
T157	14424	18	0	0
T158	7272	22	0	0
T159	4492	4	0	0
T160	13831	39	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1783	0	0
T86	3133	10	0	0
T108	15503	32	0	0
T128	11187	47	0	0
T130	5818	6	0	0
T133	8478	36	0	0
T156	7906	1	0	0
T157	14424	54	0	0
T158	7272	44	0	0
T159	4492	8	0	0
T160	13831	24	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1391	0	0
T86	3133	9	0	0
T108	15503	17	0	0
T128	11187	20	0	0
T130	5818	12	0	0
T132	4077	1	0	0
T133	8478	7	0	0
T156	7906	6	0	0
T157	14424	33	0	0
T158	7272	29	0	0
T159	4492	9	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	2111	0	0
T86	3133	8	0	0
T108	15503	30	0	0
T128	11187	53	0	0
T130	5818	22	0	0
T132	4077	20	0	0
T133	8478	23	0	0
T156	7906	8	0	0
T157	14424	61	0	0
T158	7272	22	0	0
T159	4492	3	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1647	0	0
T86	3133	5	0	0
T108	15503	32	0	0
T128	11187	20	0	0
T130	5818	14	0	0
T132	4077	4	0	0
T133	8478	16	0	0
T156	7906	17	0	0
T157	14424	90	0	0
T158	7272	34	0	0
T159	4492	1	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1492	0	0
T86	3133	2	0	0
T108	15503	20	0	0
T128	11187	12	0	0
T130	5818	5	0	0
T132	4077	10	0	0
T133	8478	1	0	0
T156	7906	12	0	0
T157	14424	36	0	0
T158	7272	6	0	0
T159	4492	9	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1508	0	0
T86	3133	5	0	0
T108	15503	27	0	0
T128	11187	16	0	0
T130	5818	17	0	0
T132	4077	3	0	0
T133	8478	16	0	0
T156	7906	5	0	0
T157	14424	65	0	0
T158	7272	3	0	0
T159	4492	6	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1452	0	0
T86	3133	1	0	0
T108	15503	23	0	0
T128	11187	26	0	0
T130	5818	9	0	0
T132	4077	6	0	0
T133	8478	11	0	0
T156	7906	4	0	0
T157	14424	79	0	0
T158	7272	8	0	0
T159	4492	7	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1470	0	0
T86	3133	1	0	0
T108	15503	31	0	0
T128	11187	19	0	0
T130	5818	8	0	0
T132	4077	3	0	0
T133	8478	5	0	0
T156	7906	2	0	0
T157	14424	50	0	0
T158	7272	31	0	0
T159	4492	9	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1528	0	0
T86	3133	9	0	0
T108	15503	28	0	0
T128	11187	13	0	0
T130	5818	7	0	0
T132	4077	2	0	0
T133	8478	10	0	0
T156	7906	12	0	0
T157	14424	25	0	0
T158	7272	33	0	0
T159	4492	6	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431957862	1453	0	0
T86	3133	7	0	0
T108	15503	22	0	0
T128	11187	22	0	0
T130	5818	9	0	0
T132	4077	5	0	0
T133	8478	6	0	0
T156	7906	2	0	0
T157	14424	24	0	0
T158	7272	31	0	0
T159	4492	2	0	0